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AM263P4: Porting FreeRTOSConfig.h settings from Cortex A to R5

Huey Duong
Intellectual 290 points
Part Number: AM263P4

Tool/software:

I'm currently porting FreeRTOS code from a Cortex A the AM263P4 R5F core.

Since the R5F core does not have a GIC, I'd like to confirmation on the settings for FreeRTOSConfig.h?

Documentation on FreeRTOS is a bit ambiguous and TI SDK examples do not define these.


ARM Cortex-R5 Xilinx UltraScale MPSoC - FreeRTOSTm  states Using FreeRTOS on ARM Cortex-A9 Embedded Processors - FreeRTOSTm  is also relevant to Cortex-R core.

Please help confirm the following settings should be left undefined:

configINTERRUPT_CONTROLLER_BASE_ADDRESS

configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET

configUNIQUE_INTERRUPT_PRIORITIES

configFPU_D32

configINTERRUPT_CONTROLLER_BASE_ADDRESS

configEOI_ADDRESS      <<< We have an address set here in our existing R5F port, but I can not find documentation on TI stating there is an EOI register

Thanks for the assistance.

  • 0 in reply to PratheeshGangadhar
    Intellectual 290 points

    Thank you for the information.  

    The decision by the company was to use non proprietary code and tools.  to use as much open source code as possible to support the transition to another MCU if necessary.  We are using GNU GCC compiler and also need to have code that supports multiple CPUs.

    In developing the code for the prior project, there is already a code for FreeRtosConfig.h that uses a more recent FreeRTOS version than the TI SDK.  Hence there are configuration settings existing in the file that I need to make work or comment out for the TI AM263P4 device.

    This is a requirement from the company. Unfortunately we can not simply use all the tools from TI (CLANG and ARM_CR5F).  I need to make the existing port work with AM263P4.

    Any help would be appreciated.  What I'm looking for is confirmation that these macros should be left undefined (not relevant) for AM263.

    thanks

  • 0 in reply to Huey Duong
    TI__Mastermind 44544 points

    Hi Huey,

    blog.freertos.org/Using-FreeRTOS-on-Cortex-A-proprietary-interrupt-controller

    Huey Duong said:
    configEOI_ADDRESS      <<< We have an address set here in our existing R5F port, but I can not find documentation on TI stating there is an EOI register

    You can refer to Register addendum to find the EIO register address.: https://www.ti.com/lit/pdf/spruj57

    Further more 

    Huey Duong said:

    Please help confirm the following settings should be left undefined:

    configINTERRUPT_CONTROLLER_BASE_ADDRESS

    configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET

    configUNIQUE_INTERRUPT_PRIORITIES

    configFPU_D32

    configINTERRUPT_CONTROLLER_BASE_ADDRESS

    configEOI_ADDRESS      <<< We have an address set he

    As far as I checked in the SDK port these are not getting used.

  • 0 in reply to Nilabh Anand
    Intellectual 290 points

    Hi Nilabh, thanks for your response.

    Can you provide a bit more clarity to your response.   I have read the blog and looked at the register addendum before posting this thread.

    Even though the blog post says it is relevant to R5, I don't think it is for the AM263P4 because it does not have a GIC, so a lot of the settings don't apply.  Which is why I wanted clarity on how to use the other settings.

    In regards to the EOI, can you provide a bit more information.  What address exactly should I be using for the FreeRTOS port for configEOI_ADDRESS?

    There are multiple EOI registers in the addendum.  Is it CFG0_INTR_ENABLE_CLEAR @ 0x50D0 101C?

    Thanks.

  • 0 in reply to Huey Duong
    TI__Mastermind 44544 points
    Huey Duong said:

    an you provide a bit more clarity to your response.   I have read the blog and looked at the register addendum before posting this thread.

    Even though the blog post says it is relevant to R5, I don't think it is for the AM263P4 because it does not have a GIC, so a lot of the settings don't apply.  Which is why I wanted clarity on how to use the other settings.

    Hi Huey, Yes, they are not required .

    Huey Duong said:

    In regards to the EOI, can you provide a bit more information.  What address exactly should I be using for the FreeRTOS port for configEOI_ADDRESS?

    There are multiple EOI registers in the addendum.  Is it CFG0_INTR_ENABLE_CLEAR @ 0x50D0 101C?

    EOI is also needed in my opinion, as the FreeRTOS port in SDK does not use it.

  • 0 in reply to Nilabh Anand
    Intellectual 290 points

    Thanks for the response.

    Just one last confirmation before I close this thread:

    Nilabh Anand said:
    EOI is also needed in my opinion, as the FreeRTOS port in SDK does not use it

    Can you confirm the address I would use for EOI is CFG0_INTR_ENABLE_CLEAR @ 0x50D0 101C?

    Thanks.

  • +1 in reply to Huey Duong
    TI__Mastermind 44544 points

    Hi Huey,

    Please see the register address below, I also checked in the freeRTOS port in SDK, we are not using it, so you can skip this also.