AM2432: SOC writing LPDDR4 timing error

What DDR configuration file are you using?  Did you use the DDR register configuration tool https://dev.ti.com/sysconfig/?product=Processor_DDR_Config&device=AM2432

to generate a DDR configuration file for your board?

Regards,

James

Hi JJD:

      We have used TI's sysconfig tool to configure LPDDR4,The problem only occurred after using sysconfig to generate a DDR profile for my board,Now I'd like you to help me identify if it's one of our parameters that is not configured correctly that is causing this problem, and what we can do to fix it.

please send the configuration file from the sysconfig tool, including the *.syscfg file.  PLease also send DDR datasheet.

Regards,

James

Hi James,

help customer upload the files. Datasheet will send via email to you.

https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/908/settings_5F00_info_5F00_AM243x_5F00_ALV_5F00_32256B_5F00_800Mhz_5F00_Inovance_5F00_0425_5F00_85C.syscfg

BR,

Biao

I noticed the .syscfg file is from v10.01 of the sysconfig tool.  Can they try with v10.02 (which is the latest on the web):  https://dev.ti.com/sysconfig/?product=Processor_DDR_Config&device=AM2432

This version enables WDQS Read Based Control (see DDR datasheet for more information) which helps ensure proper DQS timing.

Regards,

James

Hi James,

customer feedback the WDQS is no use, do you have any other suggestion to customer?

BR,

Biao 

"is no use".  does that mean they tried it and it didn't work?  Or they have no use for WDQS?

What change are they looking for?  Are they seeing a functional failure?

Regards,

James

Hi James,

Sorry for this, customer have tried it, but it does not work to this issue, I think there is no functional failure, customer are doing HW test and find this is abnormal.

BR,

Biao

Hi James,

    We have enabled the WQDS function in the current configuration, but this configuration has not improved the DDR write timing problem, we have communicated with the DDR manufacturer, they believe that the DDR read/write timing is controlled by the SOC, and suggested that we communicate with TI.

    Note:According to the current DDR configuration, the SOC is working fine (we are running the firmware in DDR), but we haven't done the high and low temperature environment test and the Memery stress test yet, and I'm worried that the above mentioned issues will cause the DDR to work abnormally.

zhanglongc,

can you explain what you see that is wrong with the write timing?  Please explain what you think needs to change.  Your scope shot is difficult to read

Regards,

James

Hi James,

pls see below explain from customer:

Good example:

Ti-AM3352BZCZ60+Winbond-W631GU6MB11I (DDR3L) - DQS edge and DQ center alignment:

Current project test waveform: TI-AM2432+ISSI-IS43LQ32256B-062BLI DQS edge and DQ edge pairs (does not meet DDR manual)

requirement from DDR datasheet:

Customer support need: Can we configure tDQS2DQ to meet the timing requirements for DDR write operations?

BR,

Biao

Hi James,

any update, pls help priority this, thanks for support.

BR,

Biao

The DQS to DQ relationship should be optimized during training.  How are you initializing the DDR?  What test code are you running when making the measurements?  Can you confirm you are performing writes when taking the scope shots?

If you are using u-boot to initialize the DDR, please add the patch as described here:

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1358039/faq-board-bring-up-tips-for-sitara-devices-am64x-am243x-am62x-am62ax-am62px#r

and post the register dump from the UART console window.

Regards,

James

Hi James,

customer is using AM2432, there is no A53 core and no uboot in their sdk, they are using R5F and MCU+ SDK only. can you share the code or patch to them to dump the register or share the address directly. 

BR,

Biao

I've attached a GEL file which can be loaded into CCS and run to collect the regdump data.  

/cfs-file/__key/communityserver-discussions-components-files/908/DDRSS_5F00_RegDump_5F00_CTLPHY.gel

Alternatively, they can dump registers 0xF308000-0x0F30D5F4, preferably in this format (addr data), like this:

0x0F308000 0x10460B01
0x0F308004 0x5D1AF3C3
0x0F308008 0x0171A610
0x0F30800C 0x40020A11
0x0F308010 0x00052006

etc.

Regards,

James

As DQS and DQ are edge rise matched, looks like there is read operation there. Not sure whether the test code have any read operation,

Hi Thomas,

Thanks for your suggestion, I will let customer double confirm it.

Hi James,

pls see the register dump from customer.

ddr register dump.txt

BR,

Biao

Something is a little strange in the regdump, it seems to be configured for 2 different frequencies, but i don't know how that happened.  Can you send the .h file that you are using for DDR configuration?

Regards,

James

Hi James,

FYI.

am243x_ddr_config.zip

BR,

Biao

Ok, i've looked at the files (the zip has two register dump labeled v10.02, so i guessing one of them is really a register dump of v10.01).  There is definitely something wrong with the v10.01.h file.  Please use v10.02.h file a run the tests again.  Also be sure you are capturing a write instead of a read.

Regards,

James

Hi James,

customer have tried this 10.02, and they make some test program to control the write DDR or read DDR using the uart console, so they can confirm this is write waveform, the issue still is here. do you have time tomorrow morning (Dallas time)? customers want to have some online discussion with you, they want to know this issue root cause: Their PCB layout issue or AM2432 LPDDR4 driver issue? I will send the calendar to you via email, you can accept it or suggest other time. let me know your available time slot.

BR,

Biao 

It appears that the DQS signal is not terminated.  Can they try with the WLS Set B setting in the tool, as shown below:

Which specific DQ and DQS signals are you probing?  What is the location of the probe points?

Regards,

James

Hi James:

    we test using v10.02.h file,I'm sure we are capturea write opertaion.

Hi James:

   1、Current，we set WLS:WL  set A,this is DDR Manufacturer Recommendation ,is that right?

   2、DQ0_A and DQS0 signals we probed,  the probe points neaser to DDR'S DQ0_A and DQS0 PINS

   3、we use dram is LPDDR4 ;

You would have to ask the DDR manufacturer what they would recommend.  I'm just asking to try with WL set B, because in past debug sessions this has helped to ensure DQS gets terminated. 

Also, i'd like to go back to understand how you are distinguishing a read vs. write.  You said previously that you are performing a test from uboot.  But uboot would also be executing out of DDR.  How are you distinguishing a code fetch vs a data write?  When do you trigger the scope?     

Regards,

James

Hi James:

   1、we perfirming test don't from uboot,we use lpddr4 test software,we send commands through uart to control the SOC to read or write operations to the LPDDR4, read and write software run in the RAM area of the SOC, when the SOC receives the command to write the LPDDR through uart, the SOC continues to write "AA55" and "55AA" to the LPDDR alternately, so that the SOC can write "AA55" and "55AA" to the LPDDR. , so as to ensure that the DQ0 signal is flipped between "1" and "0". When the SOC receives a read command through uart, the SOC reads out the written data.
   2、Can you test the waveforms of the AM2432 reading and writing LPDDR4 via the AM2432's EVM? That way I can compare your test waveforms with ours and also rule out the effect of SOC on the DDR configuration.

 Regards,

 zhanglong

Hi James:

    The DDR manufacturer recommends adjusting the tDQS2DQ parameter via the SOC side, but I didn't find in the Sysconfig tools if I set this parameter.

tDQS2DQ is not something that is adjustable in the Sysconfig tool.  This gets adjusted during training.  That's why i think there is something not completing properly in the training.  

Have you tried WL Set B?

We have performed DQS2DQ test, one example is below

Are you measuring using the differential DQS signal, or just a single ended DQS signal?

Regards,

James

Hi James:

     1、 No,Currnet we always set WL Set B,DDR The manufacturer tells me that setting it to both "WL Set B" and "WL Set A" is fine, so I'm wondering if both of these settings make a difference in how LPDDR4 writes are affected；

    2、 I measuring using the differential DQS signal,I see you DQS2DQ test waveforms,it's pretty standard and meets DDR write timing requirements, are you testing LPDDR4?

Hi zhanglong

yes, those measurements were with LPDDR4.  

Regards,

James

Hi James,

According to your suggestion, customer set WL to Set B. The test waveform is as follows. tDQS2DQ is about 300 ps, ​​but it is worse than your test waveform.

Question 1: According to JESD209-4E, half of the DQS cycle of LPDDR4 at 800MHz clock is 625us, tDQS2DQ SPEC: 200~800ps, so is the current waveform is OK?

Question 2: Are the test waveforms of AM2432 adapted to LPDDR4 from different manufacturers very different?
Question 3: can you help review the DDR configuration again? and customer want to improve the current waveform, do you have any more suggestion to them?

https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/908/ISSI_5F00_IS43LQ32256B_2D00_062BLI_2D00_LPDDR4_5F00_WL_2D00_Set_2D00_B.syscfg

Question 4: Do you need to review customer DDR layout?

BR,

Biao

Biao Li said:

Question 1: According to JESD209-4E, half of the DQS cycle of LPDDR4 at 800MHz clock is 625us, tDQS2DQ SPEC: 200~800ps, so is the current waveform is OK?

the waveforms still don't look correct.  DQS is still full swing, which means it is not getting terminated.  You may need to discuss this with the memory vendor.  Note that in our plot, both the DQ and DQS signals are terminated.

Biao Li said:

Question 2: Are the test waveforms of AM2432 adapted to LPDDR4 from different manufacturers very different?

The waveforms shouldn't be that much different.  The AM24x training algorithm should optimize the signals for optimal marginality

Biao Li said:

Question 3: can you help review the DDR configuration again? and customer want to improve the current waveform, do you have any more suggestion to them?

I reviewed the configuration, and don't see any issues.  As i mentioned, the training algorithm should center the DQS relative to DQ.

Does the other byte show the same relationship?  

Regards,

James

Hi James,

customer want loop you and lpddr4 vendor together, and have a meeting for this waveform, because DDR vendor think the waveform is ok, but you think this still abnormal, and customer also facing some random functional issue regarding LPDDR4, so I want to book your time to have a online meeting with customer and DDR Vendor. I will send the invitation to you, pls help give your available time zone to me.

BR,

Biao 

ok, i can make the call at the proposed time.  Do you have any details on the functional issues?

Regards,

James

Hi James,

the issue customer said is ecc error, it will resulting stuck or reboot. Thanks for your support.

BR,

Biao

Training results i showed on call:

****Memory VREF Training****
VREFca
CS0_A (CS0)
F2 0x2c (27.6%VDDQ = 304mV)(Rng 0) - - -

VREFdq 
CS0 
F2 0x24 (24.4%VDDQ = 268mV)(Rng 0)

***Processor VREF Training****

VREFdq
Byte 0
F2R0 0x1d (12.9%VDDQ = 142mV)(LPDDR4 Rng 0)
Byte 1
F2R0 0x1c (12.7%VDDQ = 139mV)(LPDDR4 Rng 0)

Regards,

James

Just to summarize our call from last night, the DRAM vendor explained that the waveforms were within spec based on LPDDR4 JEDEC spec (there is not the strict requirement that the DQS transition be aligned in the middle of the DQ eye at the DRAM pin), see below (tDQS2DQ=200-800ps):

We recommend customer perform DDR stress tests across application operating temp using memtester or similar DDR memory test.

Regards,

James