RM46L430: Input timing requirement

Ryoma Ohashi

Part Number: RM46L430

Tool/software:

Hi team,

According to the data sheet, the rise/fall time between VIL and VIH is specified as tin_slew=1nsmax.

Q1: Does it mean that the rise/fall time of the input voltage to the MCU has to be less than 1ns?
Q2: Do all input terminals have to meet these specifications?
Q3: If the rise/fall time exceeds 1ns, will there be a problem with the operation?

Regards
Ohashi

10 months ago

0 Brennan Hartigan 10 months ago

TI__Genius 10634 points

Ohashi,

Please expect a delayed response due to the Diwali holiday in India.

Regards,

Brennan

+1 jagadish gundavarapu 10 months ago in reply to Brennan Hartigan

TI__Guru 69891 points

Hi Ohashi,

Ryoma Ohashi said:
Q1: Does it mean that the rise/fall time of the input voltage to the MCU has to be less than 1ns?

You are correct the rise/fall time should be less than 1ns.

Ryoma Ohashi said:
Q2: Do all input terminals have to meet these specifications?

Yes, all GPIO input terminals should meet this requirement.

Ryoma Ohashi said:
Q3: If the rise/fall time exceeds 1ns, will there be a problem with the operation?

It causes additional aging on the IO cell. The longer the signal is in the mid-range of Voh/Vol, the more wear/tear is put on the voltage buffer.

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Thanks & regards,
Jagadish.

0 Ryoma Ohashi 10 months ago in reply to jagadish gundavarapu

TI__Expert 5045 points

Hi Jagadish,

Thanks for your support.

jagadish gundavarapu said:
It causes additional aging on the IO cell. The longer the signal is in the mid-range of Voh/Vol, the more wear/tear is put on the voltage buffer.

Why does the signal in the mid-range of Voh/Vol gives wear/tear on the voltage buffer??

Regards
Ohashi

+1 jagadish gundavarapu 10 months ago in reply to Ryoma Ohashi

TI__Guru 69891 points

HI Ohashi,

When the device is in an "undefined state" and may* consume much more power than usual (possibly leading to the death of the device.) This is because in this state, some circuit elements inside the chip are all "on" and create essentially a dead short between Vcc and Vss. So this condition must be avoided on most digital IC's.

Can you please refer below links once for more details:

digital logic - what happens when voltage is in indeterminate region? - Electrical Engineering Stack Exchange

Why do the TTL and CMOS circuits have indeterminate regions between 0 and 1 logic? - Quora

--
Thanks & regards,
Jagadish.

0 Ryoma Ohashi 10 months ago in reply to jagadish gundavarapu

TI__Expert 5045 points

Hi Jagadish,

Thanks for your support.

Q1: Can we use SN74LVxx series for the input signal? If not suitable, is there recommended series?

Q2: Customer feels that 1ns requirement is quite strict. Is there tips for the ciruit to satisfy this requirement? (e.g. lower parastic capacitance by making the signal line short, use smaller dumping resister, ect.)

Regards
Ohashi