AM2434: Change EtherCAT PRU Sync0 pin

Erik

Part Number: AM2434
Other Parts Discussed in Thread: SYSCONFIG

Tool/software:

Hi,

We want to use the alternative pin for the EtherCAT SYNC0 signal on a custom board but could not see the signal.

So we instead tried to verify that this works on the AM243x LP.

Using the TI beckhoff SubDevice example we can get it to run in DC sync mode and we can see the SYNC0 signal on the default pin PRG1_PRU0_GPO19/U3.

On the AM243 launch-pad the alternative pin PRG1_PRU1_GPO19/AA13 is connected to the PHYs PWDN/int pins.
So to test the alternative SYNC0 pin we disabled the PWDN functionality for the PHYs, changed SYNC0 pin in sysconfig and looked at pin AA13 with a logic analyzer.

But the behavior is not as we expected:
The PHYs are correctly configured and the SubDevice gets to DC-sync OP state. But SYNC0 signal is still seen on the default pin U3. The pin we've set in sysconf (AA13) is just pulled low and has no SYNC0 signal.

What should we change in the TI beckhoff SubDevice example to get SYNC0 on the pin we set in sysconfig?

I think maybe we need to update registers for the Time Router, but if that is the case we would be thankful for some guidance about what/how.

Thanks!

9 months ago

+1 Aaron Thomas 9 months ago

TI__Expert 8945 points

Hi Erik,

The following are the pins/signals available for mapping Sync signals to Time Sync Event Outputs for AM64x / AM243x TI EVMs:

In order to map the Sync0 signal, you will have to route it to one of the following Time Sync Event Output:
Following are the list of output pins for the above mentioned signals:
The above mentioned output pins are mapped to the following ball numbers:
Only Ball number D18 has been bought out in AM64x/AM243x EVM and connected to the pin J12. The rest of the ball numbers are not connected to any output pins.

Steps to route sync signal to J12:

Open the main.c file in the example

Add the following blocks of code in the required headers and macro definitions

/* Include Macros */

#include <drivers/hw_include/cslr_soc.h>
/* Sync Events*/
#define SYNC_OUT0                               0
#define SYNC_OUT1                               1
 
/*
 * PAD configuration for Ball.D18
 * Required to configure SYNC0_OUT as pin out
 */
static Pinmux_PerCfg_t gTsrPinMuxMainDomainCfg[] = {
    {
    PIN_ECAP0_IN_APWM_OUT,
    ( PIN_MODE(1) | PIN_PULL_DISABLE ) /* PIN_MODE 1 is SYNC0_OUT */
    }, 
 
    {PINMUX_END, PINMUX_END}     
};
 
void TSR_config(uint8_t syncSignal);

/* Function Definition and Call */

/*!
 * \brief
 *  Configuration for TSR.
 *
 * \details
 * This function configures pinmux required for TSR to route the sync signals to SYNC0_OUT pin
 *
 *  \param[in]      syncSignal      Sync0/Sync1 signal to be routed to SYNC0_OUT pin
 *
 */
void TSR_config(uint8_t syncSignal) {
    // Call Pinmux_config API to max the required changes in pinmuxing.
    Pinmux_config(gTsrPinMuxMainDomainCfg, PINMUX_DOMAIN_ID_MAIN);
    /* PRU IEP Enable SYNC MODE */
    CSL_REG32_WR(CSL_PRU_ICSSG1_PR1_CFG_SLV_BASE + CSL_ICSSCFG_IEPCLK, 1);
    CSL_REG32_WR(CSL_TIMESYNC_EVENT_INTROUTER0_CFG_BASE + 0x64, 0x0001001D + syncSignal);
}
 
int main(void)
{
    uint8_t syncEvent = SYNC_OUT0;
    /* Additional configuration to route the sync0 or sync1 signal to SYNC0_OUT PIN */
    TSR_config(syncEvent);
}

Regards,
Aaron

0 Erik 9 months ago in reply to Aaron Thomas

Prodigy 20 points

Thank you! Very comprehensive answer

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AM2434: Change EtherCAT PRU Sync0 pin