Tool/software:
Hello，I am susie.
I have a question about SPI CLK signal SI test.
There is a small step of 500 mV at the falling edge and 2.5V the rising edge.
I change sysconfig tool to config CLK Signal "pull up", but it doesn't work.
I want to know how to change the driver to increase SPI signal driving strength？
Thank you.
The figures are change sysconfig tool to "pull up" as below.
I would like to know if there is a risk of false triggering for this small step within the range of 0.8V - 2.4V?
Is it necessary for me to increase the driving strength of this SPI signals？
Yes， I reserved 0R. When I change 0R to 33R ,the test waveform is poor. The test figure is as below.
Hello
I try 22R ,but it also have this small step. The figure is as below.
I wonder if there is any risk with this waveform? Thank you.
Hello,
I am measuring at the destination. The destination is the SPI ADC chip.
We use the SPI to config ADC register.
I am measuring the SPI CS\MOSI \SCLK signal.
Here is the requirement of SPI input signal as below.
I am wonder if there is any risk with this waveform? Thank you.
