AM2434: (RG) MII back-to-back configuration

Claus Negele

Part Number: AM2434
Other Parts Discussed in Thread: TIDEP-01032,

Tool/software:

Dear TI experts,

we want to combine two TIDEP-01032 Dual Motor Controllers on a single board to build a four-axes controller.

To this end, we need to connect the two Sitara AM2434 by EtherCAT to have each of them operate as an individual EtherCAT node.

As this takes place on one board, we want to omit the PHYs between the two Sitaras and connect the RGMIIs back-to-back.

1) Are there any recommendations on how to do this?

2) Can the TIDEP-01032 PRU-ICSS EtherCAT firmware be configured to use MII instead of RGMII?

3) Is there a recommendation on how a back-to-back configuration could be achieved with MII instead of RGMII? A potential difficulty are the TXC / RXC signals, as in MII both are outputs of the PHY.

4) Can the FW be configured to run MII on one port and RGMII on the second port?

Thank you

Claus

9 months ago

0 Aaron Thomas 9 months ago

TI__Expert 8935 points

Hi,

Claus Negele said:
1) Are there any recommendations on how to do this?

To be aligned on your requirement, can you confirm if the following image depicts the same:

Claus Negele said:
2) Can the TIDEP-01032 PRU-ICSS EtherCAT firmware be configured to use MII instead of RGMII?

We do not support RGMII interface for EtherCAT. Only MII is supported.

Claus Negele said:
3) Is there a recommendation on how a back-to-back configuration could be achieved with MII instead of RGMII? A potential difficulty are the TXC / RXC signals, as in MII both are outputs of the PHY.

I'll check if this is possible for MII.

Claus Negele said:
4) Can the FW be configured to run MII on one port and RGMII on the second port?

As mentioned earlier, only MII is supported for EtherCAT.

Regards,
Aaron

0 Aaron Thomas 9 months ago

TI__Expert 8935 points

Claus Negele said:
As this takes place on one board, we want to omit the PHYs between the two Sitaras and connect the RGMIIs back-to-back.

We do not support PHY less connection between EtherCAT devices. You will be needing an external logic to manage link state as firmware needs this link state input to configure the ports correctly. Also without PHY, there will be reduction of 300ns in latency, and we can't predict the firmware impact due to this reduced latency.

Regards,
Aaron

0 Claus Negele 9 months ago in reply to Aaron Thomas

Prodigy 30 points

Hi Aaron,

thanks for your reply. Except for the two AM243x on the left and right, your picture is correct.

Understood the clarification on RGMII / MII, so it is now clear the interface is MII.

Regarding your second answer, we are aware of the link state topic, but that sound like a problem that can be handled. What exactly does the SW expect to happen in this phase? Could we e.g. use the PHY_RESETn outputs of AM243x #1 and #2 to generate the link presence signal?

Regarding the 300ns reduced latency: Isn't this a latency between two different SoCs? Is that a strong concern?

Thanks

Claus

0 Aaron Thomas 9 months ago in reply to Claus Negele

TI__Expert 8935 points

Hi Claus,

Claus Negele said:
What exactly does the SW expect to happen in this phase? Could we e.g. use the PHY_RESETn outputs of AM243x #1 and #2 to generate the link presence signal?

Just to clarify, you are intending to not use PHYs on both the TIDEP-01032 as well as on both the AM243x EtherCAT SubDevices, right?

Claus Negele said:
Regarding the 300ns reduced latency: Isn't this a latency between two different SoCs? Is that a strong concern?

This 300ns refers to the PHY latency within a single SOC (between Rx and TX). Our implementation uses PHYs so we are not sure of the firmware behavior without this PHY latency handled.

Regards,
Aaron