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MSPM0G1507: DMA single transfer latency

Munan Xu
Expert 4940 points
Part Number: MSPM0G1507

Tool/software:

Hello,

I have a customer asking if we have a similar reference to the MSP430 DMA peripheral for MSPM0 where we specify a cycle time latency for a DMA transfer. If not, what is the latency from triggering a DMA transaction to the data being transferred? Both for single transfer, and then also for block or burst transfer.

Munan

  • 0
    TI__Mastermind 46515 points

    Hi Munan,

    I checked the internal data base. However, there is no related information for DMA module in it. 

    I more thing I noticed that the DMA in MSPM0 only works in PD1 and sourced from MCLK. There will not be this much configurations as the MSP430 device. 

    Best regards,

    Cash Hao

  • 0 in reply to Cash Hao11
    TI__Expert 4940 points

    Hi Cash,

    Ok understood that there shouldn't be as many configurations as the MSP430, but we should have some sort of information on how many clock cycles it takes from a DMA trigger to transfer completion right?

    We have a pretty detailed explanation on things like ADC timing and we even have a great description of the generic event channel trigger latency, is the DMA trigger handshake the same as this? Is it a different process?

    Munan

  • 0 in reply to Munan Xu
    TI__Mastermind 46515 points

    Hi Munan,

    For my understanding, there should be no trigger latency for DMA. Since the DMA only sources from MCLK. However, the ADC issue is related to different asynchronous clock source.

    I can check with design team if we have this data for the time cycle of a DMA trigger to transfer completion.

    Best regards,

    Cash Hao

  • 0 in reply to Cash Hao11
    TI__Expert 4940 points

    Cash any update here?

    Munan