AM2432: Using common TCM section for both R5F cores

Hello Maor ,

I am looking at your queries and you may expect reply in one or two days .

Regards,

Anil.

Thanks Anil

Hello Maor ,

If you configure the R5F core in dual-core mode, then the R5F core is divided into two R5F cores (R5F0_0 and R5F0_1).

And each core has dedicated TCM A and TCM B memories and dedicated bus interfaces.

If you want to transfer data in between two R5F cores, then you can go with the IPC method rather than updating shared memories manually.

Regards,

Anil.

Hi Anil

Is there still a way to port some of the data between the cores TCMs?

Up until now I used both cores's TCM's so connection between modules in my sw was direct with 0 latency. I need to transfer real time data in the lowest possible latency. The transfer time should be less than 31.25us. Can you advise how to do that ?

Hello Maor ,

Can you please explain your use case here ?

How many bytes do you want to transfer from which memory to which memory ?

Like MSRAM/DDR to TCM .How many bytes ?

So, that I can help you .

Regards,

Anil.

I have a real time control loops, the application requires to run the control loops every 31.25us. 

Today, I found that the time critical code and data must run from the TCM. For that, the entire TCM of both R0 and R1 cores is used.

I plan to split the application so that all the control loops will run in one core and all the modules that requires the control loops services will run at the second core. I would like to keep the TCM usage untouched and use it as shared memory between the two cores. 

Is it possible to allocate the entire 128kB TCM to a single core and have the second core access it from the entire chip memory domain ?

And another thing, if each core has dedicated buses to it own TCM only when using dual core, how does it work in single core ? Does the core in use access the second core's TCM directly or via additional bus ?

Thanks

Maor

Hello Maor,

Thanks for sharing the above details.

We can implement your application in the method below.

In the linker cmd file, you need to specify what the TCM memory locations you are going to use in Core1 to share it with the core2.

Next, the control loop runs in core1 for every 31.25usec, and we need to send IPC notify to core2 as this control loop operation is done for every ~31.25usec .

Then, core2 will read the core 1 TCM memory with the Global address memory view. Please look at the below memory map table. Here , core 2 can't read the TCM local address space of core1 .

Make sure that we need to complete the 1st control loop operation in between two cores before processing for the new control loop operation.

This way you can share data in between two cores .

Steps : 

1. Define TCM memory which is shareable in between Core1 and Core2  in linker cmd file .

2. After doing control loop operation in core1, Send IPC notify to Core2

3. Read core1 TCM data through global address space and act accordingly in core 2.

The latency details of ipc notify are below. Mostly, we need to send a 32 bit value so, it takes almost ~1usec.

https://software-dl.ti.com/mcu-plus-sdk/esd/AM64X/10_00_00_20/exports/docs/api_guide_am64x/DATASHEET_AM243X_EVM.html#autotoc_md117

Maor Shalom said:

And another thing, if each core has dedicated buses to it own TCM only when using dual core, how does it work in single core ? Does the core in use access the second core's TCM directly or via additional bus ?

In the single core configuration, only one core can act and the TCM memory size is increased to 64KB from 32KB. Other than this, there is no change and the buses are the same.

Regards,

Anil.

Thanks Anil

Why do I need the IPC ? if I sync both cores interrupts so that the each core is accessing the shared memory on a specific time should I still use it ?

What is the expected latency for one core to access the other cores TCM via the global memory region ?