AM2434: AM243x-LP

Part Number: AM2434

Tool/software:

Hi There,

About AM243-LP (AM2434) , suppose I use R5FSS0-0, 0-1, 1-0, and 1-1 (i.e. use all 4 R5F cores). I understand the allocation is as follows.

core 0-0: 32KB TCMA, 16 KB TCMB0, 16 KB TCMB1
core 0-1: 32KB TCMA, 16 KB TCMB0, 16 KB TCMB1

core 1-0: 32KB TCMA, 16 KB TCMB0, 16 KB TCMB1
core 1-1: 32KB TCMA, 16 KB TCMB0, 16 KB TCMB1

Is the aforementioned allocation correct? Is it possible to have a piece of TCM (either TCMA or TCMB or both) visible to both core 0-0 and core 0-1? 


Best regards,
Jinlong

  • Hello ,

    I am looking at your queries and you may expect reply in one or two days .

    Regards,

    Anil.

  • Hello Jinjong,

    The above TCM memory allocation is fine.

    Is the aforementioned allocation correct? Is it possible to have a piece of TCM (either TCMA or TCMB or both) visible to both core 0-0 and core 0-1? 

    In the linker cmd file, you need to specify what the TCMA/TCMB memory locations you are going to use in Core1 to share it with core2.

    Next, the core1 writes data on TCM memory and after writing completion, we need to send IPC notify to core2 as this Core1 operation is done.

    Then, core2 will read the core 1 TCM memory with the Global address memory view in the IPC notify ISR routine .

    Please look at the memory map below. Here, core 2 can't read the TCM local address space of core1.

    This way, you can share data in between two cores.

    Steps : 

    1. Define TCM memory which is shareable between Core1 and Core2 in linker cmd file.

    2. After doing writing operations in core1 TCM, Core1 sends  IPC notify to Core2

    3. Read core1 TCM data through global address space in core 2.

    The latency details of ipc notify are below. Mostly, we need to send a 32-bit value, so it takes almost ~1usec.

    https://software-dl.ti.com/mcu-plus-sdk/esd/AM64X/10_00_00_20/exports/docs/api_guide_am64x/DATASHEET_AM243X_EVM.html#autotoc_md117

    Regards,

    Anil.