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AM2432: Debounce Feature Support on Pin T4, W3, C17, W5

Kevin Peng
Expert 3802 points
Part Number: AM2432

Tool/software:

Hi TI Experts,

Customer is working on AM2432 SDK9.2.

They are using pin T4 & W3 for EQEP1, and using pin C17 & W4 for EQEP2.

From the datasheet description below, we could know that EQEP1 & EQEP2 both support Debounce feature, which means that pin T4, W3, C17, and W4 support debounce feature.

However, when we look at the GPIO session, the pin T4, W3, W4, and C17 stand for GPIO1_23, GPIO1_24, GPIO1_31, and GPIO1_62 respectively shown below.

And below it clearly describes that only for those GPIO who have (1) symbol could support Debounce feature. Unfortunately, all of T4, W3, W4, and C17 do not have (1) symbol.

Actually there are two questions below from customer side.

1: For the same Pin (pin T4, W3, C17, and W4), why it could support Debounce feature when it is configured as EQEP, but not support Debounce feature when it is configured as GPIO? This does not make sense.

2: Could you please double confirm if customer using pin T4 & W3 for EQEP1, and using pin C17 & W4 for EQEP2, could customer use Debounce feature on pin T4, W3, C17, and W4?

Thanks,

Kevin

  • +1
    TI__Mastermind 47046 points

    Hello Kevin, 

    Kevin Peng said:
    1: For the same Pin (pin T4, W3, C17, and W4), why it could support Debounce feature when it is configured as EQEP, but not support Debounce feature when it is configured as GPIO? This does not make sense.

    The above query make sense.

    Long back, I had discussed with the Hw team on this, and they have confirmed that based on the Mux mode selection , the debounce period logic is selected.

    So, even pins have support for different functionality. In all MUX modes this feature is not enabled.

    And, the above pins have the debounce filter support in EQEP mode and not in the GPIO mode.

    Kevin Peng said:
    Could you please double confirm if customer using pin T4 & W3 for EQEP1, and using pin C17 & W4 for EQEP2, could customer use Debounce feature on pin T4, W3, C17, and W4?

    Yes , debounce logic is supported in EQEP mode .

    On AM64X there is only one MCU_CTRL_MMR to configure a debounce period for both PAD CFG registers and debounce selection bits available for each MAIN and MCU PAD CFG registers, either to enable debounce time or not.

    So, a total of 6 debounce registers are there to configure different debounce timings and which are belongs to MCU_CTRL_MMR registers only.

    And, each PADCFG_CTRL0_CFG0_PADCONFIG  and MCU_PADCFG_CTRL0_CFG0_PADCONFIG  has a debounce selection bits and users can configure different debounce periods from MCU_CTRL_MMR_1 to MCU_CTRL_MMR_6 and disabled also .

    Regards,

    Anil.