LP-MSPM0G3507: Cross-triggering one-shots

Tool/software:

Hey. Im trying to set up TIMA0 to cross-trigger TIMA1 for one-shots, but I must be misunderstanding something....

When TIMA1 is set up to repeat (

This does generate a one-shot on TIMA1.

So I wonder:
Why does TIMA0 generate a trigger on every compare-up events if TIMA1 is set to REPEAT=1, but not if TIMA1 is set to REPEAT=0??
What am I missing?

Here's the code:

#include <ti/driverlib/m0p/dl_interrupt.h>
#include "ti_msp_dl_config.h"

void setup();

int main(void)
{
    setup();

    while (1)
    {
    }
}

void setup()
{
    SYSCFG_DL_initPower();  // Reset & Enable power to peripherals

    // Set up the pin mux. PINCM19 = PA8, PINCM39 = PA17
    IOMUX->SECCFG.PINCM[IOMUX_PINCM19] = (IOMUX_PINCM19_PF_TIMA0_CCP0 | IOMUX_PINCM_PC_CONNECTED);
    IOMUX->SECCFG.PINCM[IOMUX_PINCM39] = (IOMUX_PINCM39_PF_TIMA1_CCP0 | IOMUX_PINCM_PC_CONNECTED);
    GPIOA->DOESET31_0 = (DL_GPIO_PIN_8 | DL_GPIO_PIN_17);

    SYSCFG_DL_SYSCTL_init();    // Enable clocks, and some system thingimabobs.


    ///////////////////////////////////// PWM setup //////////////////////////////////////
    // 1 - Clocking
    TIMA0->CLKSEL = GPTIMER_CLKSEL_BUSCLK_SEL_ENABLE;
    TIMA0->CLKDIV = GPTIMER_CLKDIV_RATIO_DIV_BY_8;
    TIMA0->COMMONREGS.CPS = 39U;

    TIMA1->CLKSEL = GPTIMER_CLKSEL_BUSCLK_SEL_ENABLE;
    TIMA1->CLKDIV = GPTIMER_CLKDIV_RATIO_DIV_BY_8;
    TIMA1->COMMONREGS.CPS = 39U;

    // 2 - CCACT            CC pin actions: High on zero, low on compare-up
    uint32_t CCACT_MASK = (GPTIMER_CCACT_01_SWFRCACT_CMPL_MASK | GPTIMER_CCACT_01_SWFRCACT_MASK |
                           GPTIMER_CCACT_01_FEXACT_MASK | GPTIMER_CCACT_01_FENACT_MASK |
                           GPTIMER_CCACT_01_CC2UACT_MASK | GPTIMER_CCACT_01_CC2DACT_MASK |
                           GPTIMER_CCACT_01_CUACT_MASK | GPTIMER_CCACT_01_CDACT_MASK |
                           GPTIMER_CCACT_01_LACT_MASK | GPTIMER_CCACT_01_ZACT_MASK);

    uint32_t actions = (GPTIMER_CCACT_01_ZACT_CCP_HIGH | GPTIMER_CCACT_01_CUACT_CCP_LOW);
    TIMA0->COUNTERREGS.CCACT_01[0] = (TIMA0->COUNTERREGS.CCACT_01[0] & ~CCACT_MASK) | (actions & CCACT_MASK);
    TIMA1->COUNTERREGS.CCACT_01[0] = (TIMA1->COUNTERREGS.CCACT_01[0] & ~CCACT_MASK) | (actions & CCACT_MASK);

    // 3 - CCCTL            Compare mode, Load COND on CCP trigger rise, updates to CC written immediately.
    uint32_t CCCTL_MASK = (GPTIMER_CCCTL_01_COC_MASK | GPTIMER_CCCTL_01_ZCOND_MASK |
                           GPTIMER_CCCTL_01_LCOND_MASK | GPTIMER_CCCTL_01_ACOND_MASK |
                           GPTIMER_CCCTL_01_CCOND_MASK);

    uint32_t mode_Conds = (GPTIMER_CCCTL_01_COC_COMPARE | GPTIMER_CCCTL_01_CCUPD_IMMEDIATELY);
    TIMA0->COUNTERREGS.CCCTL_01[0] = (TIMA0->COUNTERREGS.CCCTL_01[0] & ~CCCTL_MASK) | (mode_Conds & CCCTL_MASK);

    mode_Conds |= GPTIMER_CCCTL_01_LCOND_CC_TRIG_RISE;
    TIMA1->COUNTERREGS.CCCTL_01[0] = (TIMA1->COUNTERREGS.CCCTL_01[0] & ~CCCTL_MASK) | (mode_Conds & CCCTL_MASK);

    // 4 - OCTL             CCP Initally low, no invertion, use generator out.
    TIMA0->COUNTERREGS.OCTL_01[0] = (GPTIMER_OCTL_01_CCPIV_LOW | GPTIMER_OCTL_01_CCPOINV_NOINV | GPTIMER_OCTL_01_CCPO_FUNCVAL);
    TIMA1->COUNTERREGS.OCTL_01[0] = (GPTIMER_OCTL_01_CCPIV_LOW | GPTIMER_OCTL_01_CCPOINV_NOINV | GPTIMER_OCTL_01_CCPO_FUNCVAL);

    // 5 - IFCTL            No invert, use trigger input
    uint32_t IFCTL_MASK = (GPTIMER_IFCTL_01_INV_MASK | GPTIMER_IFCTL_01_ISEL_MASK);
    uint32_t input = (GPTIMER_IFCTL_01_INV_NOINVERT | GPTIMER_IFCTL_01_ISEL_TRIG_INPUT);
    TIMA1->COUNTERREGS.IFCTL_01[0] = (TIMA1->COUNTERREGS.IFCTL_01[0] & ~IFCTL_MASK) | (input & IFCTL_MASK);

    // 6 - LOAD         pwm period = 1000
    TIMA0->COUNTERREGS.LOAD = 1000;
    TIMA1->COUNTERREGS.LOAD = 300;

    // 7 - CTRCTL           CVAE=0,
    uint32_t CTRCTL_MASK = (GPTIMER_CTRCTL_CZC_MASK | GPTIMER_CTRCTL_CAC_MASK |
                            GPTIMER_CTRCTL_CLC_MASK | GPTIMER_CTRCTL_CVAE_MASK |
                            GPTIMER_CTRCTL_CM_MASK | GPTIMER_CTRCTL_REPEAT_MASK |
                            GPTIMER_CTRCTL_EN_MASK);

    uint32_t ctrctl_val = (GPTIMER_CTRCTL_REPEAT_REPEAT_1 | GPTIMER_CTRCTL_CM_UP | GPTIMER_CTRCTL_EN_DISABLED | GPTIMER_CTRCTL_CVAE_ZEROVAL);
    TIMA0->COUNTERREGS.CTRCTL = (TIMA0->COUNTERREGS.CTRCTL & ~CTRCTL_MASK) | (CTRCTL_MASK & ctrctl_val);

    ctrctl_val = (GPTIMER_CTRCTL_REPEAT_REPEAT_1 | GPTIMER_CTRCTL_CM_UP | GPTIMER_CTRCTL_EN_DISABLED | GPTIMER_CTRCTL_CVAE_ZEROVAL);
    TIMA1->COUNTERREGS.CTRCTL = (TIMA1->COUNTERREGS.CTRCTL & ~CTRCTL_MASK) | (CTRCTL_MASK & ctrctl_val);

    // 8 - DUTY CYCLE (compare value)
    TIMA0->COUNTERREGS.CC_01[0] = 610;
    TIMA1->COUNTERREGS.CC_01[0] = 229;

    // 9 - ENABLE CLOCK   
    TIMA0->COMMONREGS.CCLKCTL = GPTIMER_CCLKCTL_CLKEN_ENABLED;
    TIMA1->COMMONREGS.CCLKCTL = GPTIMER_CCLKCTL_CLKEN_ENABLED;

    // 10 - SET CCP DIRECTION
    TIMA0->COMMONREGS.CCPD = GPTIMER_CCPD_C0CCP0_OUTPUT;
    TIMA1->COMMONREGS.CCPD = GPTIMER_CCPD_C0CCP0_OUTPUT;

    // 11 - TRIGGER CONTROL
    TIMA0->COMMONREGS.CTTRIGCTL = (GPTIMER_CTTRIGCTL_EVTCTTRIGSEL_CCU0 | GPTIMER_CTTRIGCTL_EVTCTEN_ENABLE | GPTIMER_CTTRIGCTL_CTEN_ENABLE);

    // 12 - TSEL     Trigger select
    TIMA1->COUNTERREGS.TSEL = (TIMA1->COUNTERREGS.TSEL & ~GPTIMER_TSEL_ETSEL_MASK) | (GPTIMER_TSEL_ETSEL_TRIG0 & GPTIMER_TSEL_ETSEL_MASK);
    TIMA1->COUNTERREGS.TSEL |= (GPTIMER_TSEL_TE_ENABLED);


    TIMA0->COUNTERREGS.CTRCTL |= GPTIMER_CTRCTL_EN_ENABLED; // Start the main timer
    //TIMA0->COMMONREGS.CTTRIG = GPTIMER_CTTRIG_TRIG_GENERATE;  // Manually generate trigger
}