TDA4AL-Q1 cannot boot up at -40 degree C

Hi Kevin,

Our SoC operating temperature range is from 125C -- -40C. If you are under -40C we cannot foresee what might go wrong.

Apart from SOC there is eMMC/MMC, DDR that might also be not functional at the -40C temperature.

- Keerthy

Hi Keerthy,

Sorry for the wrong description.

The issue occurs at ambient temperature -40 degree C, which is right at the temperature boundary. 

Like I pointed out this could be very well due to DDR/eMMC/SD card not functional at that temperature.

Kevin Kuo said:

Please help analyze the reason or the component which may cause the issue.

Are you booting using SD/eMMC?

- Keerthy

Dear Keerthy,

We are booting using eMMC.

According to the datasheet, the DDR and eMMC used are both workable at -40 degree C; therefore, we need your help to give us some advices about how to figure out the root cause between these components.

Thank you.

Hi Kevin,

eMMC is not functioning well. Can you check the following things:

• Is the failing sample working at room temperatures?
• If the above is yes then can you check at what low temperature the failure is seen?
• Which eMMC is being used? Can you check with eMMC vendor on what is the probable issue?

- Keerthy

Dear Keerthy,

Please refer to the following answer:

• Is the failing sample working at room temperatures?  YES
• If the above is yes then can you check at what low temperature the failure is seen?  Will check later.
• Which eMMC is being used? Can you check with eMMC vendor on what is the probable issue?  The eMMC we used is WD/SDINBDG4-8G-ZA2.

Also, is there DDR training tool we can try on TDA4?

Hi Kevin,

I will loop in our DDR expert.

- Keerthy

Hi,

Kevin Kuo said:

Also, is there DDR training tool we can try on TDA4?

Training occurs through hardware automatically during the DDRSS / LPDDR4 initialization. If we suspect DDR, my first suggestions would be:

• Connect to the device with a debugger and try to access the DDR memory region (ex: 0x80000000) by writing values and reading them back
• Use a reduced DDR frequency to see if it impacts the failure 
• Try to increase vdd_core by 30 mV and see if it impacts the failure

Regards,
Kevin

Hi Kevin,

Could you please provide me with a method to add vdd_core in SPL?

Regards,

Luc

Dear Kevin,

Could you please provide with a method to add vdd_core in SPL?

Is there memory test tool that can help us to analyze the signal quality under different temp. ?

Thank you.

Dear Expert,

We have tried the DDR test.

Please help provide the explanation the following items:

1. Vertical and horizontal scale.

2. The meaning of the -1 error count.

3. What is the criteria for the eye diagram?

Besides, I have 3 more questions:

1. Is there any read/write action before DDR config is implemented?

2. Will the SoC adjust the DDR initialization during boot based on temperature changes?

3. Could TDA4 print out DDR training log? how?

For clear view of the eye diagram, please refer to the following:

/cfs-file/__key/communityserver-discussions-components-files/908/DDR_FB96505B3C771657_.rar

Hi, Keerthy

This is a urgent issues, customer because of this issues for product shipment pending

Could you give us some suggestion?

I also already studying the question at the same time.

Any update & related thread, I will post here :

Thank You very much

Gibbs

Related Thread, (on-going)

https://e2e.ti.com/support/processors-group/processors---internal/f/processors---internal-forum/1461031/tda4al-q1-how-to-read-the-meaning-of-ddr-eye-diagram

Hi Kevin,

Kevin Kuo said:

Besides, I have 3 more questions:

1. Is there any read/write action before DDR config is implemented?

2. Will the SoC adjust the DDR initialization during boot based on temperature changes?

3. Could TDA4 print out DDR training log? how?

1) I am not sure I understand the question. You won't be able to read or write to the LPDDR4 memory if it isn't initialized, and trying to may result in undesired behavior. Thus, you should not try to read or write to the LPDDR4 before the DDRSS initialization. 

2) I am not sure I fully understand the question. Write DQ training is sensitive to temperature; thus, it is required to re-train write DQ delays periodically to compensate for temperature changes in the system environment. The DDR register configuration tool should automatically enable periodic write DQ training starting with tool version 0.5.0 (or later). 

3) You can dump training info with the following binary. The binary should be loaded to the R5 core through CCS. Output will be provided in the CCS console window. 

tda4x_lp4_debug.zip

Regards,
Kevin

Dear Kevin,

Thank you for the reply.

Also, please help provide guideline for the dump training info.

Dear Kevin,

We have moved the debug UART port to UART9.

Please also take it into consideration.

Thank you.

Hi Kevin S

Few question,

(1) Is the binary for "DDR Margin tool"? 

(2) Base on item 1, if this is not DDR Margin tool, we may need related guide to teach us how to use it.

(3) They need source code, because they already move their "debug print out " to interface UART 9. Could you mail the source code to me?

Thank You.

Gibbs

Dear expert,

Any information update?

Besides, we have several question would like to ask.

1. According to DDR vendor' s suggestion, the ODT parameter might be different between DDRs and platforms.

   Could you help provide the ODT parameter of the TDA4AL?

   or guideline for us to measure the correct ODT option to choose.

2. What will happen if the wrong ODT parameter is used? 

3. The DDR vendor has come out a question that although the tDQSCK range in DDR setting can be set between1.5ns to 3.5ns,

    are the value 1.5ns and 3.5ns acceptable for the program or the SOC?  

4. Please help provide the guideline for dump out the DDR training info. The result might be critical for us to tune the DDR setting.

Thank you.

Kevin Kuo

Gibbs, Kevin,

Kevin S said:

3) You can dump training info with the following binary. The binary should be loaded to the R5 core through CCS. Output will be provided in the CCS console window. 

tda4x_lp4_debug.zip

The above binary does not use UART. It uses the CCS console window. In other words, terminal output is through JTAG. All you need to use this binary is JTAG , Code Composer Studio, and a compatible emulator such as XDS110. 

Kevin S said:

Training occurs through hardware automatically during the DDRSS / LPDDR4 initialization. If we suspect DDR, my first suggestions would be:

• Connect to the device with a debugger and try to access the DDR memory region (ex: 0x80000000) by writing values and reading them back
• Use a reduced DDR frequency to see if it impacts the failure 
• Try to increase vdd_core by 30 mV and see if it impacts the failure

The above steps are what I suggested for next steps and the only reply I see related is asking for help to modify vdd_core. Unfortunately, I will have to prepare a patch file if you are unsure how to do this, and this will take some time. 

Using a reduced DDR frequency should be a very quick and easy debug step and I can easily guide you to update your DDR configuration in u-boot if you do not know how to do that - it shouldn't take more than 5 to 10 minutes to update your configuration and re-build your tiboot3.bin file (no other files need to be re-built).

The same can be said for using JTAG to poke the DDR memory region after the failure occurs (which should be even easier / quicker debug step than using a reduced DDR frequency).

Regards,
Kevin

Hi Kevin,

Thank you for taking the time to help us with this.

I attempted to perform the electronic eye diagram procedure using CCS. I skipped UART initialization, and in the final step, I replaced the file with tda4x_lp4_debug.out. I tried running this on both MCU_R5 and MAIN_R5, but the console consistently displays the following message:

AutoRun: Target not run as the symbol "main" is not defined

Could you please provide me with the correct sequence of steps or configuration needed so I can successfully complete the data dump?

Regards,
Luc

Dear Kevin S.

We have tried to reach TDA4 with JTAG when the failure occurred; however, the XDS110 showed TDA4 not reachable.

Besides, let me explain the reason why we focus on the DDR.

1. We have tried ABA test method on DDR and find out that the NG phenomena follows the DDR device.

2. We have tried to compare the DDR eye diagram of NG DDR under different ambient temperature. Although XDS110 cannot reach TDA4 when the issue occurs, we still got the eye diagram of the NG DDR device under 25 degree and -25 degree since it is still bootable. The result looks quite different from the normal DDR. The normal DDR can get similar eye diagram result under 25 and -40 degree.

25 degree:

-25 degree:

3. We tried to boot from the same SD card on both normal and NG DUT and found that the NG DUT still cannot boot under -40 degree, which means that the boot device does not affect the failed phenomena. 

The above test results lead us to conclude that further verification related to DDR is required.

Hi,

Luc Tung said:

AutoRun: Target not run as the symbol "main" is not defined

When you load a binary through CCS, it will often try to "auto run" the binary and stop at the "main" function.

In this case, CCS cannot find the symbol "main", so it does not execute any code, and stops at the code entry point. This is not a concern.

All you should need to do is press the "Resume" button and the code should execute. Alternatively you can select "Run" -> "Resume" from the drop down menu. 

Regards,
Kevin

Hi,

Kevin Kuo said:

Although XDS110 cannot reach TDA4 when the issue occurs, we still got the eye diagram of the NG DDR device under 25 degree and -25 degree since it is still bootable.

The plot from the -25 degree temperature appears completely broken, implying reads / writes to DDR are not functioning correctly. When you say "since it is still bootable" (at -25 degree), do you mean that your NG board works fine at -25 degree C (with software executing from DDR)?

What happens if you boot at 25C, and then slowly decrease your temperature? 

Are you able to test with a slower DDR frequency to see if the issue goes away? 

Regards,
Kevin

Dear Kevin S.,

Yes, the NG board works fine at -25 degree C.
Do you mean that we can try to capture the eye diagram with the process, boot at 25C and slowly decrease the temperature? 
We will try and feedback to you.

We have tried to decrease the DDR frequency, but it directly cause the DUT not bootable.
Could you please help suggest which parameter should be adjusted as well besides frequency?

Thank you.

Hi,

Kevin Kuo said:

Yes, the NG board works fine at -25 degree C.

If the board works fine (software application running from DDR) , then that implies DDR is working. I don't know why the eye diagram is showing all red (only at -25C), but there must be something else contributing to that behavior (aside from temperature) if the board works fine otherwise.

Kevin Kuo said:

We have tried to decrease the DDR frequency, but it directly cause the DUT not bootable.
Could you please help suggest which parameter should be adjusted as well besides frequency?

Did you regenerate the register settings? Anytime you change DDR frequency, you need to use the DDR register configuration tool and re-generate new DDR register settings. 

What frequency(ies) did you try? What was the error? Were you booting at room temperature? 

Regards,
Kevin

Hi Kevin,

We execute the DDR dump training info program on the following 5 DDR settings at room temperature and record logs.

1. DDR config tool 0.10 + custom ddr timing setting + custom ODT setting

2. DDR config tool 0.10 + custom ddr timing setting + default ODT settings, only change to enable CK ODT Override

3. DDR config tool 0.11 + custom ddr timing setting + default ODT setting

4. DDR config tool 0.11 + custom ddr timing setting + custom ODT setting

5. DDR config tool 0.11 + custom ddr timing setting + default ODT settings, only change to enable CK ODT Override

20250203_DDR Log.zip

Could you please let me know which version we can use, or if there are any further adjustments needed?

Thank you.

Luc

Hi,

From a quick spot check from the log files, there does not appear to be much different in the trained values across the different settings.

Regards,
Kevin

Dear Kevin S,

Kevin S said:

From a quick spot check from the log files, there does not appear to be much different in the trained values across the different settings.

Should we do the experiment under -25 degree C and compare the result?  Does the result be affected by temperature?

Could you help quick explain the log to us?

Thank you.

Dear Kevin S,

We have executed the DDR dump training info program under -40 degree C.

The result looks different. Please help to have a quick look. 

Thank you.

BWLGYA004GN6ZC_20250122_ODT_DEF_ENA_CKODT_-40_degree.zip

Hi, Kevin Kuo & Luc

I need to clarify something.

Question 1 : 

I assume these 5 (parameter) experiments are works in normal temperature, isn't?

1. DDR config tool 0.10 + custom ddr timing setting + custom ODT setting

2. DDR config tool 0.10 + custom ddr timing setting + default ODT settings, only change to enable CK ODT Override

3. DDR config tool 0.11 + custom ddr timing setting + default ODT setting

4. DDR config tool 0.11 + custom ddr timing setting + custom ODT setting

5. DDR config tool 0.11 + custom ddr timing setting + default ODT settings, only change to enable CK ODT Override

Question 2 : 

Depends on your latest post for this file "BWLGYA004GN6ZC_20250122_ODT_DEF_ENA_CKODT_-40_degree.zip"

Base on "question 1" and 5 test items, what's the setting parameter for this experiments?

Does DDR work?

Thanks

Gibbs

Dear Gibbs,

Please refer to the following reply.

Gibbs Shih said:

I assume these 5 (parameter) experiments are works in normal temperature, isn't?

Yes. 

Gibbs Shih said:

Base on "question 1" and 5 test items, what's the setting parameter for this experiments?

Does DDR work?

The setting of this experiment is "DDR config tool 0.11 + custom ddr timing setting + default ODT settings, only change to enable CK ODT Override" and the DDR does not work.

Dear Kevin S. and  Gibbs,

After checking all the setting aforementioned with -40 degree C.

We found that the setting, "DDR config tool 0.10 + custom ddr timing setting + default ODT settings, only change to enable CK ODT Override," can boot normally at -40 degree C with NG DDR.

Could you help explain the reason and give us some advice about what would be affected under this configuration. Will there be any risk?  Is there other parameters should be adjusted to get better result?

The DDR configuration setting, the DDR training dump info at -40 degree, and the eye diagram at -40 degree are as following:

ddr v3.rar

If there is any more information or experiments needed for analysis, please let us know.

Thank you.

Dear Kevin S. and Gibbs,

Is there any update about the question?

Hi Kevin,

My understanding from Gibbs is that when you set CK ODT Override to "disable" (along with other changes), the issue went away. Is this the correct understanding? We also set CK ODT override to "disable" on our TI EVM. My understanding is that use of this feature is intended to be used when you have separate clocks going to each rank, which is not present on the TDA4x design.

It is okay to use v0.10.0 on TDA4AL. 

Regards,
Kevin

Dear Kevin S.,

Please let me summarize the experiment results for you:

1. DDR config tool 0.10 + custom ddr timing setting + custom ODT setting (Failed)

2. DDR config tool 0.10 + custom ddr timing setting + default ODT settings, only change to enable CK ODT Override (Pass)

3. DDR config tool 0.10 + custom ddr timing setting + default ODT setting (Pass)

4. DDR config tool 0.11 + custom ddr timing setting + default ODT setting (Failed)

5. DDR config tool 0.11 + custom ddr timing setting + custom ODT setting (Failed)

6. DDR config tool 0.11 + custom ddr timing setting + default ODT settings, only change to enable CK ODT Override (Failed)

As you can see that CK ODT is not the main reason, but the DDR config. tool version and the ODT setting; therefore, we would like to know 

1. What are the differences between v0.10.0 and v0.11.0? What will be impact if we do not update the config. tool version?

2. Since the ODT setting do have some influence to DDR, is there any improvement about ODT setting due to the training dump information and the eye diagram we provided? We would like to know the correct setting which can make sure the stability of our DUTs.

Please kindly help with the above questions.

Thank you.

Hi, Kevin Kuo

I already reply in mail loop.

Gibbs

Dear Kevin S. and Gibbs,

Thank you for the reply.

We still have one question would like to figure out.

Since the issue looks directly related to DDR setting, why the log shows different result and misleads us to eMMC device?