TMS570LC4357: Discrepancy in Clock Source Disable Clear Register (CSDISCLR) Documentation

Tool/software:

Hello,

I have been working with the Clock Source Disable Clear Register (CSDISCLR) as described in the technical reference manual. I noticed an apparent discrepancy in the documentation that I would like to clarify.

According to the documentation of the CSDISCLR register (Figure 2-19 and Table 2-31):

• For bits clearing clock sources ([7-3], [1-0]):
  • Reading 0: Clock source is enabled.
  • Writing 0: Clock source state is unchanged.
  • Reading 1: Clock source is enabled.
  • Writing 1: Sets the clock source to the enabled state.

This documented behavior where both reading 0 and 1 indicate an enabled state seems contradictory and may lead to confusion regarding the actual state of the clock source.

My assumption is by considering typical behavior for such registers:

• Reading 0 usually indicates that the clock source is enabled.
• Reading 1 usually indicates that the clock source is disabled.
• Writing 0 has no effect.
• Writing 1 enables the clock source.

My question is: Is this a documentation error, or is there a specific reason for this behavior? Could you please provide clarification or the correct way to interpret these register operations, is my assumption correct?

Thank you for your assistance.