Tool/software:
Dear TI Support,
I am currently working with the TMS570LC4357 microcontroller and came across the CSDIS (Clock Source Disable) register, particularly the capability to disable all clock sources. According to the documentation, the CSDIS register controls the state of the device clock sources.
Specific Questions:
- Purpose: What is the intended use case or purpose for the ability to disable all clock sources? Is this primarily for power-saving modes or other specific applications?
- Impacts: If all clock sources are disabled, what is the effect on the system? Specifically, how does this impact the CPU, peripherals, and interrupts?
- Recovery Mechanism: What mechanisms are in place to recover the system from a state where all clock sources are disabled? How can the system re-enable a clock source to become functional again?
- Wakeup Process: The documentation notes that on wakeup, only clock sources 0, 4, and 5 are enabled. Can you provide more details on the wakeup process and what triggers the re-enablement of these clock sources?
- Power Management: How does the capability to disable all clock sources fit within the overall power management strategy of the TMS570LC4357? Are there specific guidelines or recommended practices for using this feature to ensure system stability?
Understanding these aspects is crucial for our project and system stability. Any insights or additional documentation you could provide would be highly valuable.
Thank you for your assistance.
