Tool/software:
Hi,
I am using TMS570LS0432 in my design. I have an use case where the SW breifly disables the interrupt using using VIM register as shown in the below code.
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Tool/software:
Hi,
I am using TMS570LS0432 in my design. I have an use case where the SW breifly disables the interrupt using using VIM register as shown in the below code.
Hi Sreekanth Reddy,
This is done very breifly and is enabled right away after few lines of code. If an event occured that causes an interrupt during the disable period, will it still be registered by the CPU once it is enabled again?
Yes, it is registered by CPU once it is enabled again.
This is because we are not disabling the interrupt at peripheral right, so once the peripheral completes its interrupt allocated operation it raises the interrupt flag. So, once CPU enabled VIM again this interrupt will be processed by the CPU.
For example, consider ADC:
Let's assume we disabled the VIM interrupt for ADC but still we enabled the interrupt in peripheral level, so once the ADC performs its conversion it will raise the interrupt at peripheral level, and this interrupt flag will get cleared only in corresponding handler routine. So, once you enabled the interrupt at VIM this pending interrupt will immediately get push into the VIM and VIM will trigger the CPU to process the corresponding interrupt.
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Thanks & regards,
Jagadish.