This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Clocking problem.

Other Parts Discussed in Thread: TMS570LS3137, HALCOGEN

I am using a custom board tms570ls3137 with 16Mhz crytal.

AIthough I set up PLL1 and PLL2 the same but when I choose PLL1 for GCLK, the system work slower than PLL2.

With PLL2, I use rti to generate int at the rate of 1 Hz, clock source is 80Mhz and it blink ~= 4Hz period. 

And when I choose OSC for GCLK, the system work 2 times slower than PLL 1.

 

Please give me a reason! Thanks.

  • Hi,

    1. Please double check your setting for GCLK/VCLK/HCLK source. Here is the sample code to use PLL1 as GCLK source

        /** - Setup GCLK, HCLK and VCLK clock source for normal operation, power down mode and after wakeup */
        systemREG1->GHVSRC = (SYS_PLL1 << 24U)
                           | (SYS_PLL1 << 16U)
                           |  SYS_PLL1;

    2.  For RTI to use PLL2 as source: RTI module clock is PLL2/2

        /** - Setup RTICLK1 and RTICLK2 clocks */
        systemREG1->RCLKSRC = (1U << 24U)
                            | (SYS_VCLK << 16U)
                            | (1U << 8U) 
                            |  SYS_PRE1;

       Please check the setting for RTI up counter to make sure you can get 1Hz output

    3. To use OSC as GCLK source, please use

        /** - Setup GCLK, HCLK and VCLK clock source for normal operation, power down mode and after wakeup */
        systemREG1->GHVSRC = (SYS_PLL1 << 24U)
                           | (SYS_PLL1 << 16U)
                           |  SYS_OSC;

    Regards,

    QJ

  • I have the same problem. 

  • Hi,

    can you please elaborate a bit more on what you mean with 'the same' setup; are you doing the same values to the registers of PLL1 and PLL2, or do you mean the same settings in terms of prescaler values; may be you can share your source code for the clock setup?

    If you look to the TRM (pg 390 onwards, ch 10.6 Control Registers) you can see that PLL1 has two registers, and PLL2 has only one register; this is because PLL1 does also support frequency modulation (FM). For PLL1 you need to write to PLLCTL1 and PLLCTL2 register even you do not use the FM, because the ODPLL bitfield for PLL1 is located in PLLCTL2 (bits 11:9). For PLL2 you only have the PLLCTL3 register which includes the same relevant bit fields as PLLCTL1 but also the ODPLL bitfield (bits 31:29) for PLL2,  which is in PLLCTL2 for the PLL1 case. So from a configuration perspective  you need to write different 32bit values to PLLCTL1 (belongs to PLL1) and PLLCTL3 (belongs to PLL2).

    I also want to make you aware that or the RTI you might also need to check your settings; the finest granularity you can count is 2 HCLK cycles.

    Kind Regards,

      Rainer

     

  • I used HALCOGEN to generate the code and it seemed not to work properly. The PLL1  is set to 160Mhz just like PLL2 but when choose the PLL 2 instead of PLL1, the system worked faster many times than PLL1( a simple for loop and led blinky ). I did check the seting in systemInit() for PLL1 and I dont know what was happenning ?

    With PLL1, I did not use frequency modulation and RTI also work slower if I chooes PLL1 for VCLK or PLL1 and PRE1.

    Although it seemed to get a bit near normal operation that I expected, I found that 1s on and 1s off the led is set in RTI int worked like 2s on and 2s off.

    I use 16Mhz and 2 20p capacitors.

     

    I tried to redefined 16Mhz crytal to 10 Mhz and re-config PLL2 with new mul and div value, the system did work but according  to datasheet, the operating freqency is much higher than maximum rated frequency ??