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AM263P4-Q1: Setting SOP pins to 4S mode not working

Carwyn Griffiths
Prodigy 60 points
Part Number: AM263P4-Q1
Other Parts Discussed in Thread: AM263P4, SYSCONFIG, AM2634

Tool/software:

Hi,

I'm using the AM263P4 ZCZ_C package (AM263x pin compatible) together with the S25FL128S flash IC (same used on AM263x launchpad) on custom hardware.

I'm having issues with trying to read/write to the flash with the OSPI in 4S mode. I can read/write the bootloader and application in 1S mode without any issues, however cannot do so with the 4S OSPI settings.

Additionally, the bootloader is only loaded from flash when the SOP pins are in 1S mode, it does not work in 4S mode. This seems to suggest that the issue is in hardware, rather than software.

Can you confirm if there are any issues with running the ZCZ_C package in 4S mode or if there are compatibility issues with the flash used in previous launchpad development boards?

Thanks,

Carwyn

  • 0
    TI__Expert 3220 points

    Hi Carwyn,

    Thank you for the query.

    We are looking into this issue. Can you let us know which version of CCS, SysConfig and MCU_PLUS_SDK is being used?

    Regards,
    Rijohn

  • 0 in reply to Rijohn Pius
    Prodigy 60 points

    Hi Rijohn,

    I'm using CCS v12.8.1.00005, SysConfig v1.21.2 and MCU_PLUS_SDK for AM263Px v10.0.0.35.

    Thanks

  • 0 in reply to Kier
    Prodigy 60 points

    Hi Kier,

    The flash supports 4S flashing as we have used it previously with the AM2634 controller with SOP pins in 4S boot mode. 

    Our custom board previously used the AM2634 but that has been upgraded to the pin compatible AM263P4, using the same flash.

    Thanks

  • 0 in reply to Carwyn Griffiths
    TI__Expert 3220 points

    Hi Carwyn,


    Carwyn Griffiths said:
    Additionally, the bootloader is only loaded from flash when the SOP pins are in 1S mode, it does not work in 4S mode. This seems to suggest that the issue is in hardware, rather than software.

    We have to make sure the boot pins are properly latched and read inside the device.  Can you read the value of the boot pins from the CPU.
    You can confirm this by connecting to DAP and reading the value of MSS_TOPRCM_SOP_MODE_VALUE (0x53200024)


    Best Regards,
    Rijohn

  • 0 in reply to Rijohn Pius
    Prodigy 60 points

    Hi Rijohn,

    I've checked the value in that memory location and when setting the SOP pins in 4S and 1S configurations I get the following results:

    4S config.: Reg. value 0x00000000
    1S config.: Reg. value 0x00000002

    Thanks,

    Carwyn

  • 0 in reply to Carwyn Griffiths
    TI__Expert 3220 points

    Hi Carwyn,

    Carwyn Griffiths said:

    Hi Rijohn,

    I've checked the value in that memory location and when setting the SOP pins in 4S and 1S configurations I get the following results:

    4S config.: Reg. value 0x00000000

    Since the bootmode is latched correctly we don't suspect an issue in board at this moment.


    One of our customers have used this MX25L3233F QSPI Flash  and they were able to boot in 1s-1s-4s mode . So this confirms that there is no hardware limitations from Si perspective.

    Can you please help me with the below information:

    1. Can you please share the memory map register dump ( OSPI controller registers 0x538080xx ) and your SysConfig file.
    2. At what point do you witness the failure?

    Regards,
    Rijohn

  • 0 in reply to Rijohn Pius
    Prodigy 60 points

    Hi Rijohn,

    I've attached a memory dump for the OSPI registers and the syscfg file. 

    The failure happens at startup. In 1S mode the SBL is loaded from flash and I can see the change in current drawn by the board supply, in 4S mode it behaves the same as when the flash has been erased and there is no change in current draw. I can also load the application from flash with the SBL when the SOP pins are in 1S mode but not in 4S mode.

    Thanks,

    Carwyn

    ospi_memory_and_syscfg.zip

  • 0 in reply to Carwyn Griffiths
    TI__Expert 3220 points

    Hi Carwyn,

    Apologies for the delayed response. 

    I checked the OSPI configuration registers and looks like the couple of them needs modifications as below.

    1.  OSPI controller supports only SPI mode 0  [bits 2:1](CPHA=0, CPOL =0) in SDR. In SDR, NON-PHY mode [Bit 3] Baud rate should be /4.
    2.  Peripheral Chip Select lines should be configures 2'b00 in case of AM263P for boot. (0x00 Bits[13:10])
    3.  Data Transfer Type in Device Read Instruction Register (0x04) should be 2'10 in case of 1-1-4 mode.
    4.  Can you please elaborate on how you arrived at value = 0x64641818 for Device delay Register (0x0C) and Tap Value = 0

    Regards,
    Rijohn

  • 0 in reply to Rijohn Pius
    Prodigy 60 points

    Hi Rijohn,

    Thanks for getting back.

    I am unable to find the OSPI register details in either the TRM or register addendum to interpret the values held in memory. Can you advise on which sections of the relevant document has this information, if I'm missing it?

    Also, if registers are incorrectly configured when trying to load the SBL from flash does this suggest an issue with values held in ROM? And can this be corrected on a fitted device?

    Thanks,

    Carwyn

  • 0 in reply to Rijohn Pius
    Intellectual 295 points

    "OSPI controller supports only SPI mode 0  [bits 2:0](CPHA=0, CPOL =0) in SDR"

    This is not true. When power on the mcu, I could capture the SPI traffic on bus, which is running at SPI mode 3 (CPOL = 1, CPHA = 1). Which means RBL configured OSPI in mode 3.

    The issue is RBL cannot load code from ext flash at 4S mode. If as you said that one of your customer could boot in 1s-1s-4s mode, can we have the information of chip connections? As this is not related with our SW, it is about RBL.

  • 0 in reply to Phoenix Yin
    TI__Expert 3220 points
    Phoenix Yin said:

    "OSPI controller supports only SPI mode 0  [bits 2:0](CPHA=0, CPOL =0) in SDR"

    This is not true. When power on the mcu, I could capture the SPI traffic on bus, which is running at SPI mode 3 (CPOL = 1, CPHA = 1). Which means RBL configured OSPI in mode 3.

    Hi Phoenix,

    Thank you for correcting me. Yes, ROM does configure in SPI MODE = 3 in case of OSPI (4s) boot mode. Section 5.4.1.3.1 OSPI (4S) Bootloader Operation in AM263P TRM  explains this. And on checking the value Bit [2:1] in Octal-SPI Configuration Register (0x53808000) it is 2'b11 indicating that it is in MODE 3




    Mode 0 and Mode 3 is supported in SDR and In DDR mode, supported SPI Mode is mode 0.

    Phoenix Yin said:
    The issue is RBL cannot load code from ext flash at 4S mode. If as you said that one of your customer could boot in 1s-1s-4s mode, can we have the information of chip connections? As this is not related with our SW, it is about RBL.

    Our customers have used MX25L3233F QSPI Flash and they were able to boot in 1s-1s-4s mode.
    One difference which was observed in SW is the Quad enable bit configuration in  MX25L3233F and S25FL128S flashes.

    S25FL128S have CR[1] as the QE enable bit (Non-Volatile). We would need to set this bit from applications before  the initial boot(for the 1st time).
    Quad Data Width (QUAD) CR1[1]: When set to 1, this bit switches the data width of the device to 4 bit -Quad mode. That is, WP# becomes IO2 and HOLD# becomes IO3. The QUAD bit must be set to one when using Read Quad Out (6Bh) command.


    Can you please try configuring the Quad Enable bit as per the commands provided in section 8.5.2 Configuration Register 1 (CR1) ,section 10.3.7
    Write Registers (WRR 01h) of flash datasheet and using STIG mode in OSPI as per AM263P TRM section 13.3.3.6.4.11 OSPI Software-Triggered Instruction Generator (STIG)

    We are trying to replicate the hardware setup from our end. Our SW team will be working on this. Debug is in progress and will keep you posted on the update of debug.

    Thanks & Regards,
    Rijohn

  • 0 in reply to Carwyn Griffiths
    TI__Expert 3220 points

    Hi Carwyn,

    Carwyn Griffiths said:
    I am unable to find the OSPI register details in either the TRM or register addendum to interpret the values held in memory. Can you advise on which sections of the relevant document has this information, if I'm missing it?

    Please refer to AM263P Register Addendum Table 5-4072 for OSPI Configuration Registers. (Base address = 0x53808000) and Section 13.3.3.6 Octal Serial Peripheral Interface (OSPI) in AM263P TRM for more IP details.

    Regards,
    Rijohn

  • 0 in reply to Rijohn Pius
    Intellectual 295 points

    From the mcal Fls_Ospi.c, it shows the driver set the CR[1] to 1, so it should be cofigured correct.

  • 0 in reply to Rijohn Pius
    Prodigy 60 points

    Hi Rijohn,

    Thanks for clarifying on the register documentation.

    Rijohn Pius said:
     Can you please elaborate on how you arrived at value = 0x64641818 for Device delay Register (0x0C) and Tap Value = 0

    For the test I used the sbl_ospi_am263px-cc_r5fss0-0_nortos_ti-arm-clang project, modified for the flash we are using (according to syscfg file sent previously). The SBL image is placed in external flash and the SOP pins placed in 4S mode. 

    I have repeated the test with SOP pins in both 4S and 1S mode and attached the memory values. The device delay register in 1S mode is 0x0A0A0A0A.

    Thanks,

    Carwyn

    Fullscreen OSPI_4S_1S.txt Download 
    1S mode:

0x53808000	80083841	00000003	00000002	0A0A0A0A	00000025	00101002	0000003F
0x5380801C	00000000	00000000	00000000	00000200	00000000	00000001	00000001
0x53808038	000340FF	FFFFFFFF	00000000	00000000	00000000	00000000	00000000
0x53808054	00000000	00000000	00000000	00000000	00000000	00000000	00000000
0x53808070	00000000	FFFFFFFF	00000000	00000000	0000000F	00000000	00000000
0x5380808C	00000000	658A0000	00800004	00000000	00000000	000000FF	00000000
0x538080A8	00000000	00000000	00000000	00000000	00800000	00FF81F9	00000000
0x538080C4	00000000	00000000	00000000	00000000	00000000	00000000	00000000
0x538080E0	0302FA00	06F90000	00000000	00000000	00000000	00000000	00000000
0x538080FC	03000300


4S mode:

0x53808000	80083806	0802006B	00000002	64641818	00000025	00101002	00000080
0x5380801C	00000000	00000000	00000000	00000200	00000000	00000001	00000001
0x53808038	00010005	FFFFFFFF	00000000	00000040	00000000	00000000	00000000
0x53808054	00000000	00000000	00000000	00000000	00000000	00000000	00000000
0x53808070	00000000	FFFFFFFF	00000000	00000000	0000000F	00000000	00000000
0x5380808C	00000000	9FB00000	00000000	00000000	00000000	6FC20009	00000000
0x538080A8	00000000	00000000	00000000	00000000	00800000	00FF81F9	00000000
0x538080C4	00000000	00000000	00000000	00000000	00000000	00000000	00000000
0x538080E0	13EDFA00	06F90000	00000000	00000000	00000000	00000000	00000000
0x538080FC	03000300

  • 0 in reply to Carwyn Griffiths
    TI__Expert 3220 points

    Hi Carwyn,

    Thank you for the reply,

    Can you please write value 0x3580001 at Flash Command Control Register (Using STIG) register (offset = 0x90) and observe the value at Flash Command Read Data Register (Lower) (offset = 0xA0).

    This is to read the value of CR1 to ensure that Quad Enable bit is set correctly.

    Best Regards,
    Rijohn

  • 0 in reply to Rijohn Pius
    TI__Expert 3220 points

    Hi Carwyn,

    Apologies for the delay in response. 

    I recreated setup on AM263x Control Card + AM263P_ZCZ_C Si. And for me the RBL is reaching at the SBL Confirming RBL boot is successful and no HW issues.

    Here I had flashed the sbl image and hello_world app image  in mcu_plus_sdk_am263x_10_01_00_31 using AM2634 and then changed the sample to AM263Px. And booted in OSPI (4s) boot mode. PC location = 0x7012BA84 indicating RBL boot is successful.



    We are working with the SDK team internally to check for the support of this QSPI flash in SBL. I will get back on this before End of Week.

    Thanks & Regards,
    Rijohn

  • 0 in reply to Rijohn Pius
    Prodigy 60 points

    Hi Rijohn,

    Thanks for the update. 

    If your SDK team is able to test OSPI read and write to the flash in 4S mode that would prove useful in finding out what our problem is here. 

    I have attempted to read the value of CR1 using the memory browser in CCS by writing 0x3580001 to address 0x53808090 and checking the value in 0x538080A0 but the value does not seem to update and remains at 0x6FC20009. Am I using the correct method to read this register or have I missed/misunderstood some steps?

    Thanks,

    Carwyn

  • +1 in reply to Carwyn Griffiths
    Prodigy 60 points

    Hi Rijohn,

    I have managed to perform a read of the CR1 register in flash and found that the quad enable bit is not set. I have also performed a write of this bit only and found that this resolves the issue and the SBL in now loaded in 4S mode.

    It appears that the SDK does not set the quad enable bit when running on this flash in factory default state. I have been configuring the flash driver in sysconfig to the same settings as used for the flash on the am2634 launchpad, so would expect it to be behave the same. Can you confirm on your hardware whether this bit is being set by the SDK and you're seeing the same fault?

    Thanks,

    Carwyn

  • 0 in reply to Carwyn Griffiths
    TI__Expert 3220 points

    Hi Carwyn,

    Carwyn Griffiths said:
    I have also performed a write of this bit only and found that this resolves the issue and the SBL in now loaded in 4S mode.

    Glad to hear that the SBL issue is resolved at your end. It was indeed a good learning we got from this.


    Thanks & Regards,
    Rijohn