Other Parts Discussed in Thread: HALCOGEN
Tool/software:
Issue: The application does not run after being downloaded through the bootloader,
but it works correctly when downloaded via JTAG for debugging.
Bootloader Environment:
MPU: RM57L843
IDE: CCS (Code Composer Studio)
Bootloader Base Code: UART_Bootloader_RM57.zip (from the TI forum)
HL_sys_link.cmd file is as follows.
-------------------------------------
/*----------------------------------------------------------------------------*/
/* Memory Map */
MEMORY
{
/* USER CODE BEGIN (2) */
#if 1
VECTORS (X) : origin=0x00000000 length=0x00000020 vfill = 0xffffffff
FLASH0 (RX) : origin=0x00000020 length=0x001FFFE0 vfill = 0xffffffff
FLASH1 (RX) : origin=0x00200000 length=0x00200000 vfill = 0xffffffff
STACK (RW) : origin=0x08000000 length=0x00002000
RAM (RWX) : origin=0x08002000 length=0x0007E000
#else
VECTORS (X) : origin=0x00000000 length=0x00000020
FLASH0 (RX) : origin=0x00000020 length=0x001FFFE0
FLASH1 (RX) : origin=0x00200000 length=0x00200000
STACKS (RW) : origin=0x08000000 length=0x00001500
RAM (RW) : origin=0x08001500 length=0x0007EB00
#endif
/* USER CODE END */
... (rest omitted)...
-------------------------------------
The bootloader executes the void _c_int00(void) function, and then in the main function,
it jumps to the application program area as follows:
IntMasterIRQDisable();
g_ulTransferAddress = (uint32_t)APP_START_ADDRESS;
((void (*)(void))g_ulTransferAddress)();
The APP_START_ADDRESS is 0x00020020.
//--------------------------------------------------------------------------
Application Environment
MPU : RM57L843
IDE : IAR
RM57L843_flash.icf file is as follows.
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x00020020;
/*-Memory Regions-*/
define symbol __ICFEDIT_region_ROM_start__ = 0x00020040;
define symbol __ICFEDIT_region_ROM_end__ = 0x003FFFFF;
define symbol __ICFEDIT_region_RAM_start__ = 0x08001800;
define symbol __ICFEDIT_region_RAM_end__ = 0x0807FFFF - 0x00004000;
define symbol __ICFEDIT_region_shRAM_start__ = __ICFEDIT_region_RAM_end__ + 1;
define symbol __ICFEDIT_region_shRAM_end__ = 0x0807FFFF;
/*-Sizes-*/
define symbol __ICFEDIT_size_cstack__ = 0xE00;
define symbol __ICFEDIT_size_svcstack__ = 0x200;
define symbol __ICFEDIT_size_irqstack__ = 0x200;
define symbol __ICFEDIT_size_fiqstack__ = 0x200;
define symbol __ICFEDIT_size_undstack__ = 0x200;
define symbol __ICFEDIT_size_abtstack__ = 0x200;
define symbol __ICFEDIT_size_heap__ = 0;
/**** End of ICF editor section. ###ICF###*/
define symbol __region_app_code_start__ = __ICFEDIT_intvec_start__;
define symbol __region_app_code_end__ = __ICFEDIT_region_ROM_end__;
/* Define a memory region that covers the entire 4 GB addressible space of the processor. */
define memory mem with size = 4G;
/* Define a region for the on-chip Flash. */
define region ROM_region = mem:[from __region_app_code_start__ to __region_app_code_end__];
/* Define a region that corresponds to the total size reserved for the stacks.
* NOTE: It is imperative that the total stack size here matches exactly the
* total of the stack sizes used by the HALCoGen generated file sys_core.asm */
define symbol __total_stack_size__ = __ICFEDIT_size_cstack__ +
__ICFEDIT_size_svcstack__ +
__ICFEDIT_size_fiqstack__ +
__ICFEDIT_size_irqstack__ +
__ICFEDIT_size_abtstack__ +
__ICFEDIT_size_undstack__;
define region STACK = mem:[from 0x08000000 size __total_stack_size__];
/* Define a region for the on-chip SRAM - the RAM start address must be adjusted
* to accommodate the STACK region. */
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
define symbol __region_DRAM_start__ = 0x80000000;
define symbol __region_DRAM_end__ = 0x807FFFFF;
define region DRAM_region = mem:[from __region_DRAM_start__ to __region_DRAM_end__];
/* Define a block of memory to be used as the heap - note that SafeRTOS does not use the heap. */
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
/* Indicate that the read/write values should be initialized by copying from Flash. */
initialize by copy { readwrite };
/* Indicate that the noinit values should be left alone. */
do not initialize { section .noinit };
/* Define a block for the vectors and kernel's functions. */
/* define block __kernel_functions_block__ with alignment = 0x8000, size = 0x8000 */
define block __kernel_functions_block__ with alignment = 0x4, size = 0x8000
{
readonly section .intvecs,
section __kernel_functions__
};
/* Place the interrupt vectors at the required address, followed by the kernel's functions. */
place at address mem:__ICFEDIT_intvec_start__ { block __kernel_functions_block__ };
/* Place the remainder of the read-only items into Flash. */
place in ROM_region { readonly };
/* Define a block for the kernel's data. */
define block __kernel_data_block__ with alignment = 0x800, size = 0x800
{ section __kernel_data__ };
/* Define a block for the Timer Demo data. */
define block __idle_task_data_block__ with alignment = 0x20, size = 0x20
{
section __idle_task_data__,
section __idle_task_zero_data__
};
/* Place the kernel's data at the start of SRAM (immediately after the stacks). */
/* place at start of RAM_region { block __kernel_data_block__ }; */
place in RAM_region {
readwrite,
block __kernel_data_block__,
block __idle_task_data_block__,
block HEAP
};
/* seta define */
define region shRAM_region = mem:[from __ICFEDIT_region_shRAM_start__ to __ICFEDIT_region_shRAM_end__];
define block __seta_shared_block__ with alignment = 0x4000, size = 0x4000
{
section __seta_shared_RAM__
};
place in shRAM_region
{
block __seta_shared_block__
};
place in DRAM_region { section DRAM };
/* Export symbols required by c code. */
export symbol __ICFEDIT_intvec_start__;
export symbol __ICFEDIT_region_ROM_start__;
export symbol __ICFEDIT_region_ROM_end__;
define symbol lnkStartFlashAddress = __ICFEDIT_intvec_start__;
define symbol lnkEndFlashAddress = __ICFEDIT_region_ROM_end__;
export symbol lnkStartFlashAddress;
export symbol lnkEndFlashAddress;
HL_sys_startup.c 파일의 초기화 부분은 아래와 같다.
void _c_int00(void)
{
register resetSource_t rstSrc;
/* USER CODE BEGIN (5) */
/* USER CODE END */
/* Initialize Core Registers to avoid CCM Error */
_coreInitRegisters_();
/* Initialize Stack Pointers */
_coreInitStackPointer_();
/* Reset handler: the following instructions read from the system exception status register
* to identify the cause of the CPU reset.
*/
rstSrc = getResetSource();
switch(rstSrc)
{
case POWERON_RESET:
/* Initialize L2RAM to avoid ECC errors right after power on */
_memInit_();
/* Add condition to check whether PLL can be started successfully */
if (_errata_SSWF021_45_both_plls(PLL_RETRIES) != 0U)
{
/* Put system in a safe state */
handlePLLLockFail();
}
/*SAFETYMCUSW 62 S MR:15.2, 15.5 <APPROVED> "Need to continue to handle POWERON Reset" */
case DEBUG_RESET:
case EXT_RESET:
/* USER CODE BEGIN (6) */
/* USER CODE END */
/* Initialize L2RAM to avoid ECC errors right after power on */
if(rstSrc != POWERON_RESET)
{
_memInit_();
}
/* Enable CPU Event Export */
/* This allows the CPU to signal any single-bit or double-bit errors detected
* by its ECC logic for accesses to program flash or data RAM.
*/
_coreEnableEventBusExport_();
/* USER CODE BEGIN (10) */
/* USER CODE END */
/* Check if there were ESM group3 errors during power-up.
* These could occur during eFuse auto-load or during reads from flash OTP
* during power-up. Device operation is not reliable and not recommended
* in this case. */
if ((esmREG->SR1[2]) != 0U)
{
esmGroup3Notification(esmREG,esmREG->SR1[2]);
}
/* Initialize System - Clock, Flash settings with Efuse self check */
systemInit();
/* USER CODE BEGIN (11) */
/* USER CODE END */
/* Enable IRQ offset via Vic controller */
_coreEnableIrqVicOffset_();
/* Initialize VIM table */
vimInit();
/* USER CODE BEGIN (12) */
/* USER CODE END */
/* Configure system response to error conditions signaled to the ESM group1 */
/* This function can be configured from the ESM tab of HALCoGen */
esmInit();
/* USER CODE BEGIN (13) */
/* USER CODE END */
break;
case OSC_FAILURE_RESET:
break;
case WATCHDOG_RESET:
case WATCHDOG2_RESET:
break;
case CPU0_RESET:
/* Enable CPU Event Export */
/* This allows the CPU to signal any single-bit or double-bit errors detected
* by its ECC logic for accesses to program flash or data RAM.
*/
_coreEnableEventBusExport_();
break;
case SW_RESET:
break;
default:
break;
}
/* USER CODE BEGIN (22) */
#if 1 /* for bootLoader */
systemInit();
_coreEnableIrqVicOffset_();
vimInit();
esmInit();
#endif
/* USER CODE END */
_mpuInit_();
/* call the application */
__cmain();
}
