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MSPM0G3507-Q1: HFCLK_IN to CPUCLK and MCLK in RUN0 mode

David Van Vels
Prodigy 100 points
Part Number: MSPM0G3507-Q1
Other Parts Discussed in Thread: SYSCONFIG

Tool/software:

I am using an external crystal oscillator which is input on HFCLK_IN. How is this clock setup and divided to be used as the MCLK & CPUCLK in RUN0 mode?

Should this external clock frequency be 16MHz or 32MHz? If the external clock is 16MHz, can the MCLK & CPUCLK also be 16MHz?

This is a low power design that doesn't need to be run at high speed so I am looking for a reasonable power & clock setting. There is one CAN channel that is run at 1 MHz, a DAC output, a PWM output, and

a few PIO discretes. That's it.

Do you have any examples on setting this up? I am referring to page 132 of the technical manual.

I would like to run < 24MHz to avoid wait states.

Do I even need an external clock oscillator? It seems the internal SYSOSC is quite accurate. Could use the user trimmed 16MHz or 24MHz? What is the advantage of an external oscillator driving the HFCLK_IN?

  • +1
    TI__Mastermind 24215 points

    Hi David,

    David Van Vels said:
    How is this clock setup and divided to be used as the MCLK & CPUCLK in RUN0 mode?

    You can use the sysconfig tool for the clock generation.

    The input range should be 4-48MHz.

    And you can use the PLL to generate the proper MCLK or directly generate MCLK.

    David Van Vels said:
    Do you have any examples on setting this up?

    You can use sysconfig tool to generate one.

    David Van Vels said:
    Do I even need an external clock oscillator?

    Waht the CAN data bit rate? If it is smaller, for example 100ksps or 125ksps, it could work.

    While higher data bit rate will requires external high accuracy clock to reduce Error frame.

    David Van Vels said:
    Could use the user trimmed 16MHz or 24MHz?

    You need a high accuracy clock to trim the SYSOSC. If you could do this, for example, trim the SYSOSC by an high accuracy input clock, it could work.

    B.R.

    Sal