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TM4C1294NCPDT: SSI Configuration issue faced with enabling GPIO Pull Up

Vasudevan Kannan
Prodigy 75 points
Part Number: TM4C1294NCPDT

Tool/software:

Im trying to follow this note form the datasheet,

"if the SSIClk signal is programmed to steady state High through the SPO bit in the SSICR0 register, then software must also configure the GPIO port pin corresponding to the SSInClk signal as a pull-up in the GPIO Pull-Up Select (GPIOPUR) register."

These lines did not give me the desired result, the GPIOPUR regitser sets the bit 0 and it gets reset to 0 on the next lines of code.
GPIOUnlockPin(GPIO_PORTQ_BASE, GPIO_PIN_0); //unlock the pin for write access to commit reg

GPIOPadConfigSet(GPIO_PORTQ_BASE, GPIO_PIN_0, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD_WPU);

I have also tried by manipulating registers directly,

HWREG(GPIO_PORTQ_BASE + GPIO_O_LOCK) = GPIO_LOCK_KEY;
HWREG(GPIO_PORTQ_BASE + GPIO_O_CR) |= GPIO_PIN_0;

HWREG(GPIO_PORTQ_BASE + GPIO_O_PUR) |= GPIO_PIN_0;

This is snippet from SPI Module intialisation which is configured to mode 3, SPO =1, SPH = 1.

complete code,

void clock_init(){
ui32SysClock = SysCtlClockFreqSet((SYSCTL_XTAL_25MHZ|SYSCTL_USE_PLL|SYSCTL_OSC_MAIN|SYSCTL_CFG_VCO_160),40000000);
}

void SPI_init(){
/*
* 360 NW uses the SSI3 Module of TM4CNCPDT controller
* By default only SPI mode can be used in SST26VF032B SPI flash
* SST26VF032B/SST26VF032BA -> MAX CLOCK 104 MHz / 80 MHz
*/
clock_init();
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOQ);
while(!SysCtlPeripheralReady(SYSCTL_PERIPH_GPIOQ)); //wait for enable
GPIOPinConfigure(GPIO_PQ0_SSI3CLK);
GPIOPinConfigure(GPIO_PQ1_SSI3FSS);
GPIOPinConfigure(GPIO_PQ2_SSI3XDAT0); //Tx
GPIOPinConfigure(GPIO_PQ3_SSI3XDAT1); //Rx
SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI3);
while(!SysCtlPeripheralReady(SYSCTL_PERIPH_SSI3)); //wait for enable
GPIOUnlockPin(GPIO_PORTQ_BASE, GPIO_PIN_0); //unlock the pin for write access to commit reg
// Unlock the port by using the device LOCK key
//
// HWREG(GPIO_PORTQ_BASE + GPIO_O_LOCK) = GPIO_LOCK_KEY;
//
// //
// // Commit the pin to keep it in GPIO mode
// //
// HWREG(GPIO_PORTQ_BASE + GPIO_O_CR) |= GPIO_PIN_0;
//
// HWREG(GPIO_PORTQ_BASE + GPIO_O_PUR) |= GPIO_PIN_0;
// to ensure clock is sharp for falling edge, since sck is pulled up in Spi flash
GPIOPadConfigSet(GPIO_PORTQ_BASE, GPIO_PIN_0, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD_WPU);
GPIOPinTypeSSI(GPIO_PORTQ_BASE,GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3);
SSIConfigSetExpClk(SSI3_BASE, ui32SysClock, SSI_FRF_MOTO_MODE_3, SSI_MODE_MASTER, 10000000, 8);
SSIEnable(SSI3_BASE);
}

How to solve this?

  • +1
    TI__Guru**** 190616 points
    Vasudevan Kannan said:
    These lines did not give me the desired result, the GPIOPUR regitser sets the bit 0 and it gets reset to 0 on the next lines of code.

    I think you call GPIOPinTypeSSI after you call GPIOPadConfigSet. In GPIOPinTypeSSI, it will overwrite to your setting for GPIO_PIN_TYPE_STD_WPU to GPIO_PIN_TYPE_STD.  See below. You should swap the two lines.

    void
    GPIOPinTypeSSI(uint32_t ui32Port, uint8_t ui8Pins)
    {
    //
    // Check the arguments.
    //
    ASSERT(_GPIOBaseValid(ui32Port));

    //
    // Make the pin(s) be peripheral controlled.
    //
    GPIODirModeSet(ui32Port, ui8Pins, GPIO_DIR_MODE_HW);

    //
    // Set the pad(s) for standard push-pull operation.
    //
    GPIOPadConfigSet(ui32Port, ui8Pins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD);

    Vasudevan Kannan said:

    GPIOUnlockPin(GPIO_PORTQ_BASE, GPIO_PIN_0); //unlock the pin for write access to commit reg

    GPIOQ0 pin is NOT a special pin. There is no need of the unlock operation.

    Vasudevan Kannan said:
    This is snippet from SPI Module intialisation which is configured to mode 3, SPO =1, SPH = 1.

    Normally when you configure for SSI_FRF_MOTO_MODE_3, the SSI module will assert SSICLK high when in Idle even if you configure the IO pad for GPIO_PIN_TYPE_STD_WPU but I guess you what did is ok.