MSP432E401Y: MSP432E401Y and SDRAM shematic via EPI interface

Hi,

albgarc2014 said:

1-) Can I use the W9825G6KH-6 memory? Is it compatible with the EPI interface?

I don't see an issue interfacing with EPI.

albgarc2014 said:

2-) I attach the connection diagram between the SDRAM memory and the MSP432E401Y. Is the attached schematic correct? Note EPI0S0-12 is shared between address bus and data bus, while EPI0S13-14 is shared between data bus and bank select. Is this correct?

I don't see a problem as far as EPI0S0-12 and EPI0S13-14 connections. 

There is a TI Reference Design with TM4C129 and SDRAM where you can find the schematic, layout and software collaterals.

https://www.ti.com/tool/TIDM-TM4C129XSDRAM

albgarc2014 said:

3-) Does the schematic require additional components such as termination resistors or something else (I am referring only to the part related to the memory)?

No termination resistors are called for but please follow the best practices as outlined in the System Design Guideline.

4.11 External Peripheral Interface (EPI)

The MSP432E4 device supports the EPI with a dedicated 8-, 16-, or 32-bit parallel bus. The EPI has a variety of memories and peripherals that can work with the EPI module.

4.11.1 Single SDRAM In SDRAM mode, the maximum frequency is 60 MHz. Pins used for this mode are EPIOS0 to EPIOS19 and EPI0S28 to EPI0S31 (see the device-specific data sheet for the SDRAM signal functions).

4.11.2 Host Bus Mode Host bus supports 8- and 16-bit interfaces used in SRAM, PSRAM, and NOR flash memory. EPI0S0 is the LSB of the address and should be connected to A0 of 16-bit memories. The three main strobes are Address Latch Enable (ALE), Write (WRn), and Read (RDn), and the polarity of these pins can be configured in software. Depending on the mode, all of the EPI pins may be used (EPI0S0 to EPI0S35). See the MSP432E4 SimpleLink Microcontrollers Technical Reference Manual for more information on how these signals are used in the various modes.

4.11.3 Routing Considerations In EPI mode, the MSP432E4 device pins are characterized with a 35-pF output capacitance. To maintain timing margins over the full operating speed of the EPI module, EPI signal capacitance, including both load and trace capacitance, must be 35 pF or less, and the GPIO drive strength must be configured for 8 mA. Additionally, when EPI0S31 is used as a high-speed clock pin, it must be configured to 12 mA to maintain timing margins. It is not necessary to include the MSP432E4 device pin and pad characteristics when evaluating total capacitance. Limit total trace length to 6 in (15.24 cm) for full operating speed. Make an effort to keep trace lengths for clock and data similar lengths and give the clock signal 2x width spacing from other signals to avoid crosstalk.

HI,

albgarc2014 said:

I have rotated the RAM so that EPI0-14 go first through go first to A0-12,BS0-1 and then go through DQ0-15. I have equalized the line delays so that the signals up to A0-12,BS0-1 have a delay of 300ps (approximately 50mm) and continue to DQ00-15 with a delay of 173ps (approximately 15mm). I show the idea in the attached schematic.
1-) Is the idea of the schematic correct?
2.) Although the memory is 166MHz it will work at 60 MHz which is the speed of the EPI bus ?

  I don't see an issue. 

albgarc2014 said:

This is the pin assignment I selected for the EPI bus, is it correct? My doubt is because each EPI bus signal can be connected to two pins of the MCU, I am not clear if connecting a signal to one of the pins forces the rest of the signals to connect to a specific pin. Note that the DK-TM4C129X uses for EPIS030 PP3 different from my design (PN3).

You can use EPI0S30 from either PP3 or PN3. If you use PN3 for EPI0S30 then you can use PP3 for GPIO or other functions shown the mux table. 

Refer to the sdram.c example at C:\ti\TivaWare_C_Series-2.2.0.295\examples\peripherals\epi\sdram.c. This example actually PN3 for EPI0S30. 

//
// EPI0S29 ~ EPI0S30: N2 ~ 3
//
ui32Val = HWREG(GPIO_PORTN_BASE + GPIO_O_PCTL);
ui32Val &= 0xFFFF00FF;
ui32Val |= 0x0000FF00;
HWREG(GPIO_PORTN_BASE + GPIO_O_PCTL) = ui32Val;

albgarc2014 said:

Another question that has arisen in reviewing the schematics. In the DK_TM4C129X_SDRAM schematic they use the signals EPIS0-19, EPIS028-31, however in the DK-TM4C129X they only use EPIS0-15, EPIS030, EPIS034. Shouldn't they use the same EPI signals to connect both boards to run the SDRAM? Please check the attached images. 

The DK-TM4C129X EVM board uses the EPI for Host-16 interface, not SDRAM. 

albgarc2014 said:

Is the pin assignment I am implementing correct? Can I keep EPI0S0-3 assigned to PH0-3 and keep the rest of the signals the same as TI's example?

Hi,

  There is no issue to use PH0-3 for EPI0S0-3. You can use either PH0-3 or PK0-3 for EPI0S0-3.