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MCU-PLUS-SDK-AM243X: Arm-based microcontrollers forum

Anand S
Prodigy 65 points
Part Number: MCU-PLUS-SDK-AM243X
Other Parts Discussed in Thread: SYSCONFIG

Tool/software:

Subject: Inquiry Regarding Frame Check Sequence (FCS) in AM243x LaunchPad ICSSG Layer 2 Dual MAC Example

 Following my exploration of the AM243x LaunchPad's ICSSG Layer 2 dual MAC example using the latest SDK, I've successfully transmitted and received Ethernet packets via laptop using Colasoft Packet Builder.  However, I'm unable to locate functions within the Enet LLD for Frame Check Sequence (FCS) verification or utilization.  Furthermore, the `EthFrame` structure lacks FCS or CRC members.  Could you clarify why FCS isn't implemented in this structure?  Are there any functions or settings to enable FCS calculation and usage?

 EthFrame structure:

  • 0
    TI__Mastermind 27290 points

    Hi ,

    Thanks for your query.

    I will check on this and get back to you.

    Regards

    Ashwani

  • +1 in reply to Ashwani Goel
    TI__Intellectual 1145 points

    Hello Anand,

    The PRU_ICSSG's  MII_G_RT module supports by default

    • CRC32 generation on TX path
    • CRC32 checker on RX path

    Please refer to section 6.4.11.2.2.4 Receive CRC Computation and 6.4.11.2.2.5 Transmit CRC Computation of the Technical reference Manual (TRM) here: https://www.ti.com/lit/ug/spruim2h/spruim2h.pdf?ts=1737100005165&ref_url=https%253A%252F%252Fwww.ti.com%252Fproduct%252FAM2434

    • Whenever a CRC error is detected by MII_G_RT on the received frame the following hardware statistics counter is incremented.
      6.4.14.12 PRU_MII_G_RT_MII_G_RT Registers
      MII_G_RT_RX_STAT_CRC_ERR_PRU0         RX CRC Error Frame Count (PRU0)
      MII_G_RT_RX_STAT_CRC_ERR_PRU1         RX CRC Error Frame Count (PRU1)

    • This hardware statistics can be viewed on the UART terminal by entering menu option 's' to print the statistics with the ICSSG Layer 2 example.
      Alternatively, the above register's address can be monitored via the Memory Browser in CCS.

    • During transmit of the frame, the CRC is computed and inserted into the outgoing frame at the MII_G_RT module.

    Thus, FCS/ CRC is not implemented in the 'EthFrame' structure since it's automatically computed by the ICSSG MII GRT module on receive and transmit of frames. This CRC computation is enabled by default and the statistics of number of RX CRC error frames can be obtained from the above memory-mapped registers. The Enet LLD only deals with the header and payload. 

    Thanks and Regards,
    Miriam

  • 0 in reply to Miriam Santhosh Kadavan
    Prodigy 65 points

    Hi, 

    Thank you for your response.

      Regarding the ICSSG Layer 2 example, are we definitively utilizing the MII_G_RT module?  I question this because my sysconfig review reveals no discernible settings for the MII_G_RT module.

  • 0 in reply to Anand S
    TI__Intellectual 1145 points

    Hello Anand,

    Yes, the MII_G_RT module is definitively being used, else there would be no transmission or reception of packets at all.
    The RGMII / MII signals can also be observed in SysConfig:
     

    The section you have mentioned is only a placeholder that comes under the "Additional ICSS Settings" and this is not used in the generated files in the default example.

    Thanks and Regards,
    Miriam