• State
  • Locked Locked
  • Replies 1 reply
  • Subscribers 30 subscribers
  • Views 119 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Original question:

TMS570LC4357: Clarification Required on EMAC(0xFCF78000)->SOFTRESET(0x174) Behavior Affecting MDIO Module

TMS570LC4357: Rationale for RTICLK1 and VCLK Clock Source Requirements in TMS57

mc b
Prodigy 165 points
Part Number: TMS570LC4357

Tool/software:

Hello,

If it is not under NDA, could you please explain the rationale behind the following note in the TMS570 TRM (SPNU563A–March 2018 , page 144) ?

"NOTE: Selecting a clock source for RTICLK1 that is not VCLK When the application chooses a clock source for the RTICLK1 domain that is not VCLK, then the application must ensure that the resulting RTICLK1 frequency is less than or equal to the VCLK frequency divided by 3. The application can configure the RTI1DIV field of the RCLKSRC register to divide the selected clock source frequency by 1, 2, 4, or 8 to meet this requirement."

Specifically, what is the reason for this requirement, and what could potentially happen if the RTI clock frequency is set to be greater than the VCLK frequency divided by 3?

Thank you.

  • 0
    TI__Guru 69891 points

    Hi mc b,

    I don't find any explanation for this in anywhere but on my understanding, this could be due to following reason.

    If RTICLK1 is not from VCLK, that means the corresponding RTICLK1 frequency is asynchronous with VCLK.

    Example you can select External Clocks also for RTICLK1:

    So, if your RTICLK1 is asynchronous with VLCK means it also asynchronous with our core clock (GCLK).

    Because VCLK is always derived from VCLK.

    Now assume if you are operating RTICLK1 frequency same as VCLK frequency, in this case it is difficult for core to detect the RTICLK1 interrupt before it finishes its clock period right (as both are operating at same frequency), this is the reason the RTICLK frequency should always be lower than the VCLK. For example, if RTICLK frequency is 1/3 of VCLK frequency then core can easily detect the RTI interrupts before RTI clock ends its cycle.

    --
    Thanks & regards,
    Jagadish.