Other Parts Discussed in Thread: SEGGER, MSPM0L2228
Tool/software:
Hello,
I'm trying to move my project from CCS to our internal development environment, based on Segger's J-Link and related tools, like Ozone and J-Flash.
I removed all the jumpers from J14, except GND and 3V3, then connected my J-Link directly to NRST, SWDIO, SWDCLK of j14, 3V3 of J1 and GND of J2.
If I try to program the microcontroller using Ozone, I get the following message
Ozone console:
3:52:37.416 339 Debug.Start();
3:52:37.467 172 Device "MSPM0L2228" selected.
3:52:37.470 422 InitTarget() start
3:52:37.472 934 DAP initialized successfully.
3:52:37.473 004 Setting up LPM debug bits
3:52:37.475 226 InitTarget() end - Took 3.05ms
3:52:37.475 284 Found SW-DP with ID 0x6BA02477
3:52:37.478 092 DPIDR: 0x6BA02477
3:52:37.478 116 CoreSight SoC-400 or earlier
3:52:37.478 123 Scanning AP map to find all available APs
3:52:37.478 133 AP[5]: Stopped AP scan as end of AP map has been reached
3:52:37.478 140 AP[0]: AHB-AP (IDR: 0x84770001, ADDR: 0x00000000)
3:52:37.478 147 AP[1]: MEM-AP (IDR: 0x002E0001, ADDR: 0x01000000)
3:52:37.480 685 AP[2]: JTAG-AP (IDR: 0x002E0000, ADDR: 0x02000000)
3:52:37.480 700 AP[3]: MEM-AP (IDR: 0x002E0003, ADDR: 0x03000000)
3:52:37.480 705 AP[4]: MEM-AP (IDR: 0x002E0002, ADDR: 0x04000000)
3:52:37.480 715 Iterating through AP map to find AHB-AP to use
3:52:37.488 659 AP[0]: Core found
3:52:37.488 697 AP[0]: AHB-AP ROM base: 0xF0000000
3:52:37.488 709 CPUID register: 0x410CC601. Implementer code: 0x41 (ARM)
3:52:37.488 719 Found Cortex-M0 r0p1, Little endian.
3:52:37.488 728 FPUnit: 4 code (BP) slots and 0 literal slots
3:52:37.488 737 CoreSight components:
3:52:37.488 746 ROMTbl[0] @ F0000000
3:52:37.488 756 [0][0]: E00FF000 CID B105100D PID 000BB4C0 ROM Table
3:52:37.488 769 ROMTbl[1] @ E00FF000
3:52:37.488 781 [1][0]: E000E000 CID B105E00D PID 000BB008 SCS
3:52:37.498 378 [1][1]: E0001000 CID B105E00D PID 000BB00A DWT
3:52:37.498 401 [1][2]: E0002000 CID B105E00D PID 000BB00B FPB
3:52:37.498 407 [0][2]: 40402000 CID B105900D PID 001BB932 MTB-M0+
3:52:37.498 917 Connected to target device.
3:52:37.498 931 J-Link/J-Trace serial number: 602002504
3:52:37.531 026 ResetTarget() start
3:52:37.531 056 DAP initialized successfully.
3:52:37.531 065 ResetTarget() end - Took 5.58ms
3:52:37.531 069 Device specific reset executed.
3:52:37.531 207 Elf.GetBaseAddr(); // returns 0x0
3:52:37.532 132 Target.ReadU32 (0x00000000); // returns 0x4, data is 0x20208000
3:52:37.532 305 Target.SetReg ("SP", 0x20208000);
3:52:37.532 414 Elf.GetEntryPointPC(); // returns 0x3F58
3:52:37.532 564 Target.SetReg ("PC", 0x3F58);
3:52:39.590 818 Timeout while preparing target, RAMCode did not respond in time!
3:52:39.590 818 Failed to perform RAMCode-sided Prepare()
3:52:39.590 895 Download failed: J-Link reports an unspecified download error
If I try to program with J-Flash I get the following log:
Opening data file [myFile.hex] ...
- Data file opened successfully (23631 bytes, 4 ranges, CRC of data = 0x1FDCD7BF, CRC of file = 0x0F5E1964)
Programming and verifying target (23631 bytes, 4 ranges) ...
- Connecting ...
- Connecting via USB to probe/ programmer device 0
- Probe/ Programmer firmware: J-Link V12 compiled Dec 4 2024 17:53:50
- Probe/ Programmer S/N: 602002504
- Device "MSPM0L2228" selected.
- Target interface speed: 4000 kHz (Fixed)
- VTarget = 3.322V
- InitTarget() start
- DAP initialized successfully.
- Setting up LPM debug bits
- InitTarget() end - Took 3.00ms
- Found SW-DP with ID 0x6BA02477
- DPIDR: 0x6BA02477
- CoreSight SoC-400 or earlier
- Scanning AP map to find all available APs
- AP[5]: Stopped AP scan as end of AP map has been reached
- AP[0]: AHB-AP (IDR: 0x84770001, ADDR: 0x00000000)
- AP[1]: MEM-AP (IDR: 0x002E0001, ADDR: 0x01000000)
- AP[2]: JTAG-AP (IDR: 0x002E0000, ADDR: 0x02000000)
- AP[3]: MEM-AP (IDR: 0x002E0003, ADDR: 0x03000000)
- AP[4]: MEM-AP (IDR: 0x002E0002, ADDR: 0x04000000)
- Iterating through AP map to find AHB-AP to use
- AP[0]: Core found
- AP[0]: AHB-AP ROM base: 0xF0000000
- CPUID register: 0x410CC601. Implementer code: 0x41 (ARM)
- Found Cortex-M0 r0p1, Little endian.
- FPUnit: 4 code (BP) slots and 0 literal slots
- CoreSight components:
- ROMTbl[0] @ F0000000
- [0][0]: E00FF000 CID B105100D PID 000BB4C0 ROM Table
- ROMTbl[1] @ E00FF000
- [1][0]: E000E000 CID B105E00D PID 000BB008 SCS
- [1][1]: E0001000 CID B105E00D PID 000BB00A DWT
- [1][2]: E0002000 CID B105E00D PID 000BB00B FPB
- [0][2]: 40402000 CID B105900D PID 001BB932 MTB-M0+
- Executing init sequence ...
- Executing Reset (0, 0 ms)
- ResetTarget() start
- DAP initialized successfully.
- ResetTarget() end - Took 4.62ms
- Device specific reset executed.
- Initialized successfully
- Target interface speed: 4000 kHz (Fixed)
- Found 1 JTAG device. Core ID: 0x6BA02477 (None)
- Connected successfully
- Checking if selected data fits into selected flash sectors.
- ERROR: Selected Data (0x20200000 - 0x202005D0) does not fit into selected flash sectors.
More information on this can be found on the SEGGER Wiki:
wiki.segger.com/UM08003_JFlash
Disconnecting ...
- OnDisconnectTarget() start
- OnDisconnectTarget() end - Took 816us
- Disconnected
Environment:
- WIn 10
- Ozone 3.38c
- J-Flash 8.12a
- Ti ARM CLANG 3.2.2
Linker file:
/*****************************************************************************
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*****************************************************************************/-uinterruptVectors--stack_size=256
MEMORY{ FLASH (RX) : origin = 0x00000000, length = 0x00040000 SRAM (RWX) : origin = 0x20200000, length = 0x00008000 BCR_CONFIG (R) : origin = 0x41C00000, length = 0x000000FF BSL_CONFIG (R) : origin = 0x41C00100, length = 0x00000080}
SECTIONS{ .intvecs: > 0x00000000 .text : palign(8) {} > FLASH .const : palign(8) {} > FLASH .cinit : palign(8) {} > FLASH .pinit : palign(8) {} > FLASH .rodata : palign(8) {} > FLASH .ARM.exidx : palign(8) {} > FLASH .init_array : palign(8) {} > FLASH .binit : palign(8) {} > FLASH .TI.ramfunc : load = FLASH, palign(8), run=SRAM, table(BINIT)
.vtable : > SRAM .args : > SRAM .data : > SRAM .bss : > SRAM .sysmem : > SRAM .stack : > SRAM (HIGH)
.BCRConfig : {} > BCR_CONFIG .BSLConfig : {} > BSL_CONFIG}
