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MSPM0L1305: DACCTL, contradictory definitions in TRM slau847d

Rainald Koch
Intellectual 610 points
Part Number: MSPM0L1305

Tool/software:

In order to let the COMP output control the selection between DACCODE0 and DACCODE1 (for hysteresis), the DACCTL bit in CTL2 should be 1 according to Sect. 15.2.8 but 0 according to Sect. 15.3.24. Which one is correct. I already have submitted document feedback.

  • +1
    TI__Genius 10470 points

    Hello Rainald,

    I have doubled check it. In fact, in the chapter 15.2.7, it also mentioned that setting 0 to the DACCTL bit in the CTL2 register is to let COMP output control the selection of DACCODE0 and DACCODE1.

    Then I double checked it in the SDK, it also shows that setting 0 to the DACCTL bit in the CTL2 register is to let COMP output control the selection of DACCODE0 and DACCODE1.

    Please take the SDK as reference. And I will submit Jira to fix the error in the Sect. 15.2.8 of TRM.

    Much thanks to point this error.

    Best Regards,

    Janz Bai

  • 0 in reply to Janz Bai
    TI__Genius 10470 points

    Hello Rainald,

    Just add a notice. Because I will go home tomorrow for Chinese New Year so if you have further questions, please add it here after 5th February. Thanks.

    Best Regards,

    Janz Bai