Tool/software:
Hi,
I want to configure the UART and see in the block diagram in chapter "18.1.3 Functional Block Diagram" 3 possible clock sources: SYSCLK, MFCLK, LFCLK.
Then in chapter "18.2.1 Clock Control" the SYSCLK is not mentioned but then BUSSCLK. This is confusing.
The SYSCLK and BUSSCLK are not mention in the chapter "2.3 Clock Module (CKM)". Why?
Regards, Holger