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RTOS and partitioning TMS570

Raj Varada
Prodigy 170 points
Other Parts Discussed in Thread: HALCOGEN

I had a couple of questions regarding TMS570 partitioning and the RTOS it supports. My intent is two have two partitions which run two applications and have a message exchange between the two. Let me be more specific on what I intend to do. This is for an aerospace application which uses DO-178B. I intend to have one partition running a Level A application and one a Level C application. FYI Level indicates the levels of safety, level A being highest and level E being lowest level of safety. Questions I have is

 

1) What RTOS is currently supported by TMS570.

2)Can I partition the internal memory  or is memory partitioning supported only in external memory. Reason I ask this is in MPC565 we cannot parttion internal memory, hence we had to switch to external memory in past experience. Note: I understand we have MPU, however this is only for protection and not partitioning.

3)In case I cannot partition intenrnal memory can I have one application (i.e. one partition) run in internal memory and the other application run in external memory. However this seems cumbersome switching between internal and external memory.

My basic idea is to have two applications and have the RTOS schedule and run them periodically.

-Raj

  • 0
    Prodigy 170 points

    I am still looking forward for a response from TI/others, it has been 8 days since I have posted this.

    Appreciate any responses.

    -Raj

  • 0
    Prodigy 125 points

    Rajesh Varada said:

    1) What RTOS is currently supported by TMS570.

    Hi Rajesh,

    This link could answer your first question: http://www.ti.com/mcu/docs/mcuorphan.tsp?contentId=68909#realtimeopsys

    The HalCoGen tool is able to generate code with FreeRTOS (try version 2.11 it has better support).

    regards,

    Yasuki.

  • 0 in reply to 1757001
    Prodigy 170 points

    I am not sure if Free RTOS is qualified for use in Aerospace. I see that it is a SIL3 certified.

    I sitill look forward for a response to my questions(all parts) from TI.

     

    -Raj

  • 0
    TI__Mastermind 49120 points

    Hi Rajesh,

    I am sorry it has taken us this long to get our first response to you. Please find some answers embedded in the message below. I have contacted our system safety experts to comment on the application memory partitioning questions.

    1) What RTOS is currently supported by TMS570.

    >> You can find a list of some of the RTOS that support the TMS570LS microcontrollers at http://www.ti.com/mcu/docs/mcuprodtoolsw.tsp?sectionId=95&tabId=2836&familyId=1931&toolTypeId=1.

    2)Can I partition the internal memory  or is memory partitioning supported only in external memory. Reason I ask this is in MPC565 we cannot parttion internal memory, hence we had to switch to external memory in past experience. Note: I understand we have MPU, however this is only for protection and not partitioning.

    3)In case I cannot partition intenrnal memory can I have one application (i.e. one partition) run in internal memory and the other application run in external memory. However this seems cumbersome switching between internal and external memory.

    My basic idea is to have two applications and have the RTOS schedule and run them periodically.

    Best regards,

    Sunil

  • 0 in reply to Sunil Oak
    Prodigy 170 points

    Guys,

    Could I have a response to the lingering question. It's been  like more than 10 weeks.

     

    -Raj

  • 0 in reply to Raj Varada
    TI__Mastermind 23000 points

    Raj,

    I believe the past authors thought they had fully answered your question.

    In any case, the MPU found in the ARM devices is built into the CPU.  Therefore it has the capability to partition memory anywhere in the CPU's address range.  This could be internal memory/peripherals or external memory/peripherals. 

    There is not a standard definition of partitioning vs. protection across end equipment applications and microcontroller architectures.  So that we are speaking in the same terms, how do you define protection vs. partitioning?

    Regards,

    Karl

  • 0 in reply to KGreb
    Prodigy 170 points

    Karl,

    Thanks for the response.

    Protection and Partition has a difference as far as I understood from reading the TI manuals. My understanding is that we have an MPU. This guarantees that the area of memory accessed by one peripheral is not accesed by another peripheral. E.g memory of one SPI device is not accessed by another device. However what I am specifically looking for is something on the following lines. Assume

    1) We have two executables flashed into two regions of the controller internal Flash memory say R1 for  Region-1 and R2 for Region2.

    2)Say we configure the Reset Vector such that at POR we always transfer to R1.

    3)R1 is a cyclic software executed every time period  say "T", once every cycle if  say Discrete-1 and Discret-2 are simultaneously active, then only we would like to transfer the controller from R1 to R2 and not otherwise.

    4)What I mean by partitioning is that, if for some reason when I am in R1 and  Discrete-1 and Discret-2 are inactive,  I force the PC to R2, the code in R2 should not even be accessed/executed and  hence I surely know that the control can never go to R2 inadvertently. (Just assume I have additional logic when Discrete-1 and Discrete-2 are active).

    R1 and R2 in a real world scenario would be a Control software controlling say an Engine/ Brakes or whatever and R2 would be software to update Control Software, only in maintenance modes.  

    The above scenario I was explaining was actually the intent of the original question

    2)Can I partition the internal memory  or is memory partitioning supported only in external memory. Reason I ask this is in MPC565 we cannot parttion internal memory, hence we had to switch to external memory in past experience. Note: I understand we have MPU, however this is only for protection and not partitioning

  • 0 in reply to Raj Varada
    TI__Mastermind 23000 points

    Hi Raj,

    The peripherals in the Hercules platform have indepedent memories per peripheral.  It is not possible for one SPI to access the buffer memory of another SPI.  This is fixed partitioning of memory and is not related to MPU. 

    Bus masters in the device, including CPU, FlexRay, and N2HET have memory protection units.  These devices can access shared memory (TCM SRAM on R4) and each has an independent master based memory protection.  It is possible that the protection regions overlap if they are not programmed properly to insure independence.  None of the bus masters in this system are limited to support only a certain memory range - the full 4GB of address space could be supported.

    When we look at the CPU's memory protection, the ARM core follows the OSEK memory protection model.  There is an inherent expectation that the operating system is trusted and that the operating system is responsible to change the configuration of the CPU MPU as part of the task change context switch.  If this is done, I understand the CPU MPU meets the definition of partitioning that you list.

     

    Regards,
    Karl

     

     

  • 0 in reply to KGreb
    Prodigy 170 points

    Yes I agree with the statement about the inherent expectation that the OS is to be trusted. However, in our current Architecture we do not use any OS. Hence I do not think it is a possibility to do partitioning the way I envisioned earlier.

    -Raj

  • 0 in reply to Raj Varada
    TI__Mastermind 23000 points

    Hi Raj,

    I'm sorry to hear that this is not working in the way you would expect.  This style of memory protection/partitioning with software assistance for task switching is a core element of the ARM architecture and out of a silicon provider's control.  If you come back to this and wish assistance in the software implementation we will be glad to help further.

    Regards,

    Karl