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MSP432E401Y: Reading analog output from INA210 with MSP432E401Y

Part Number: MSP432E401Y
Other Parts Discussed in Thread: INA210,

Tool/software:

Hello Team,

We have connected a INA210 output voltage pin with PD4 pin of MSP432E401Y micro-controller to measure the voltage and current.

The PD4 pin is a AIN7(Analog-to-digital converter input 7).With MAP_GPIOPinTypeADC, we can configure PD4 as ADC. But I'm not finding any configuration specific to input 7 channel.

Can you please tell how to configure the AIN7 with driverlib?

Thank you.

  • Hi,

      Below is an example for configuring AIN7. 

        //
        // The ADC0 peripheral must be enabled for use.
        //
        SysCtlPeripheralEnable(SYSCTL_PERIPH_ADC0);
    
        //
        // For this example ADC0 is used with AIN7 on port D4.
        // The actual port and pins used may be different on your part, consult
        // the data sheet for more information.  GPIO port D needs to be enabled
        // so these pins can be used.
        // TODO: change this to whichever GPIO port you are using.
        //
        SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOD);
    
        //
        // Select the analog ADC function for these pins.
        // Consult the data sheet to see which functions are allocated per pin.
        // TODO: change this to select the port/pin you are using.
        //
        GPIOPinTypeADC(GPIO_PORTD_BASE, GPIO_PIN_4);
    
        //
        // Enable sample sequence 3 with a processor signal trigger.  Sequence 3
        // will do a single sample when the processor sends a signal to start the
        // conversion.  Each ADC module has 4 programmable sequences, sequence 0
        // to sequence 3.  This example is arbitrarily using sequence 3.
        //
        ADCSequenceConfigure(ADC0_BASE, 3, ADC_TRIGGER_PROCESSOR, 0);
    
        //
        // Configure step 0 on sequence 1.  Sample channel 8 (ADC_CTL_CH8) in
        // single-ended mode (default) and configure the interrupt flag
        // (ADC_CTL_IE) to be set when the sample is done.  Tell the ADC logic
        // that this is the last conversion on sequence 1 (ADC_CTL_END).  Sequence
        // 3 has only one programmable step.  Sequence 1 and 2 have 4 steps, and
        // sequence 0 has 8 programmable steps.  Since we are only doing a single
        // conversion using sequence 1 we will only configure step 0.  For more
        // information on the ADC sequences and steps, reference the datasheet.
        //
        ADCSequenceStepConfigure(ADC0_BASE, 1, 0, ADC_CTL_CH7 | ADC_CTL_IE |
                                 ADC_CTL_END);
    
        //
        // Since sample sequence 1 is now configured, it must be enabled.
        //
        ADCSequenceEnable(ADC0_BASE, 1);
    
        //
        // Clear the interrupt status flag.  This is done to make sure the
        // interrupt flag is cleared before we sample.
        //
        ADCIntClear(ADC0_BASE, 1);