Other Parts Discussed in Thread: TMDSCNCD263P, UNIFLASH
Tool/software:
Hello,
Our TMDSCNCD263P board will be in an enclosure in a high voltage environment. As a result we cannot easily reach the board and change the boot mode.
Granted, the instructions here (AM263Px MCU+ SDK: TI Uniflash Tool) mention to put the device into DevBoot mode. However, in practice I have been able to flash in QSPI(1S) mode using the onboard XDS110 debug emulator for months until very recently, irrespective of the instruction to use DevBoot. Therefore, I've not been concerned about the need to change the boot mode switches.
My problem is that now, for some reason, it is now failing as shown below:
[10/02/2025, 17:13:12] [INFO] Cortex_R5_0: GEL Output: ***OnTargetConnect() Launched*** [10/02/2025, 17:13:12] [INFO] Cortex_R5_0: GEL Output: AM263Px Initialization Scripts Launched. Please Wait... [10/02/2025, 17:13:12] [INFO] Cortex_R5_0: GEL Output: AM263Px_Cryst_Clock_Loss_Status() Launched [10/02/2025, 17:13:12] [INFO] Cortex_R5_0: GEL Output: Crystal Clock present [10/02/2025, 17:13:12] [INFO] Cortex_R5_0: GEL Output: AM263Px_SOP_Mode() Launched [10/02/2025, 17:13:12] [INFO] Cortex_R5_0: GEL Output: SOP MODE = 0x00000002 [10/02/2025, 17:13:12] [INFO] Cortex_R5_0: GEL Output: QSPI - 1S Functional boot mode [10/02/2025, 17:13:12] [INFO] Cortex_R5_0: GEL Output: AM263Px_Read_Device_Type() Launched [10/02/2025, 17:13:12] [INFO] Cortex_R5_0: GEL Output: EFuse Device Type Value = 0x000000AA [10/02/2025, 17:13:12] [INFO] Cortex_R5_0: GEL Output: AM263Px_dual_or_lockstep_mode() Launched [10/02/2025, 17:13:12] [INFO] Cortex_R5_0: GEL Output: r5fss0 = 0x00000101 [10/02/2025, 17:13:12] [INFO] Cortex_R5_0: GEL Output: r5fss1 = 0x00000000 [10/02/2025, 17:13:12] [INFO] Cortex_R5_0: GEL Output: R5FSS0 is in Lockstep mode [10/02/2025, 17:13:12] [INFO] Cortex_R5_0: GEL Output: R5FSS1 is in Dual core mode [10/02/2025, 17:13:12] [INFO] Cortex_R5_0: GEL Output: MSS_CTRL Control Registers Unlocked [10/02/2025, 17:13:12] [INFO] Cortex_R5_0: GEL Output: MSS_TOP_RCM Control Registers Unlocked [10/02/2025, 17:13:12] [INFO] Cortex_R5_0: GEL Output: MSS_RCM Control Registers Unlocked [10/02/2025, 17:13:12] [INFO] Cortex_R5_0: GEL Output: MSS_IOMUX Control Registers Unlocked [10/02/2025, 17:13:12] [INFO] Cortex_R5_0: GEL Output: TOP_CTRL Control Registers Unlocked [10/02/2025, 17:13:12] [INFO] Cortex_R5_0: GEL Output: *** R5FSS0 Reset DualCore *** [10/02/2025, 17:13:12] [INFO] Cortex_R5_0: GEL Output: ***R5FSS1 Reset DualCore *** [10/02/2025, 17:13:12] [INFO] Cortex_R5_0: GEL Output: R5F ROM Eclipse [10/02/2025, 17:13:12] [INFO] Cortex_R5_0: GEL Output: R5FSS0_0 Released [10/02/2025, 17:13:12] [INFO] Cortex_R5_0: GEL Output: R5FSS0_1 Released [10/02/2025, 17:13:12] [INFO] Cortex_R5_0: GEL Output: R5FSS1_0 Released [10/02/2025, 17:13:12] [INFO] Cortex_R5_0: GEL Output: R5FSS1_1 Released [10/02/2025, 17:13:12] [INFO] Cortex_R5_0: GEL Output: L2 Mem Init Complete [10/02/2025, 17:13:12] [INFO] Cortex_R5_0: GEL Output: MailBox Mem Init Complete [10/02/2025, 17:13:12] [INFO] Cortex_R5_0: GEL Output: *********** R5FSS0/1 Dual Core mode Configured******** [10/02/2025, 17:13:12] [INFO] Cortex_R5_0: GEL Output: SYS_CLK DIVBY2 [10/02/2025, 17:13:12] [INFO] Cortex_R5_0: GEL Output: DPLL_CORE_HSDIV0_CLKOUT0 selected as CLK source for R5FSS & SYS CLKs [10/02/2025, 17:13:12] [INFO] Cortex_R5_0: GEL Output: CLK Programmed R5F=400MHz and SYS_CLK=200MHz [10/02/2025, 17:13:12] [INFO] Cortex_R5_0: GEL Output: *** Enabling Peripheral Clocks *** [10/02/2025, 17:13:12] [INFO] Cortex_R5_0: GEL Output: Enabling RTI[0:3] Clocks [10/02/2025, 17:13:12] [INFO] Cortex_R5_0: GEL Output: Enabling RTI_WDT[0:3] Clocks [10/02/2025, 17:13:12] [INFO] Cortex_R5_0: GEL Output: Enabling UART[0:5]/LIN[0:5] Clocks [10/02/2025, 17:13:12] [INFO] Cortex_R5_0: GEL Output: Enabling QSPI Clocks [10/02/2025, 17:13:12] [INFO] Cortex_R5_0: GEL Output: Enabling I2C Clocks [10/02/2025, 17:13:12] [INFO] Cortex_R5_0: GEL Output: Enabling TRACE Clocks [10/02/2025, 17:13:12] [INFO] Cortex_R5_0: GEL Output: Enabling MCAN[0:3] Clocks [10/02/2025, 17:13:12] [INFO] Cortex_R5_0: GEL Output: Enabling MMCSD Clocks [10/02/2025, 17:13:12] [INFO] Cortex_R5_0: GEL Output: Enabling MCSPI[0:4] Clocks [10/02/2025, 17:13:12] [INFO] Cortex_R5_0: GEL Output: Enabling CONTROLSS Clocks [10/02/2025, 17:13:12] [INFO] Cortex_R5_0: GEL Output: Enabling CPTS Clocks [10/02/2025, 17:13:12] [INFO] Cortex_R5_0: GEL Output: Enabling RGMI[5,50,250] Clocks [10/02/2025, 17:13:12] [INFO] Cortex_R5_0: GEL Output: Enabling XTAL_TEMPSENSE_32K Clocks [10/02/2025, 17:13:12] [INFO] Cortex_R5_0: GEL Output: Enabling XTAL_MMC_32K Clocks [10/02/2025, 17:13:12] [INFO] Cortex_R5_0: GEL Output: ***All IP Clocks are Enabled*** [10/02/2025, 17:13:12] [INFO] Cortex_R5_0: Writing Flash @ Address 0x60000000 of Length 0x00007ff0 [10/02/2025, 17:13:33] [ERROR] Cortex_R5_0: Run failed... [10/02/2025, 17:13:33] [ERROR] Cortex_R5_0: File Loader: Memory write failed: Timed out waiting for target to halt while executing am263px_flasher.out
As you can see in the log, UniFlash has no problem connecting to the device. I have tried UNIFLASH 8.7 through to 9.0,
I hope you can appreciate that having to change the boot mode from QSPI(1S) -> DevBoot -> QSPI(1S) is wholly impractical for us.
My first request: Please advise why (in principle) the SOC cannot be flashed in QSPI(1S) mode. This might offer some clues as to how I can rescue the situation.
