This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

AM2432: DDR ECC fault injection testing issues

Part Number: AM2432

Tool/software:

Hello expert:
We are conducting fault injection testing for DDR ECC, and according to the safety manual requirements, this measure is implemented periodically.
Implementation method: Refer to the DDR ECC error injection program (ddr_ecc_test_main_ esm) in mcu_plus_std_am243x_09_00_00_00_35, perform error injection periodically, and clear the error flag and correct the error in the interrupt response.

There are the following issues
1. Performing error injection requires setting the ECC-IN bit, but TRM states that this bit must remain static before using DDR, which contradicts the need to configure the ECC-IN bit during the injection process. How should I periodically execute this diagnostic measure?


2. If an error is only injected during initialization and not corrected in the interrupt program, and triggered during periodic execution, we find that the interrupt can be entered normally when the error is triggered for the first time, but it will continue to enter the interrupt program after being triggered once. Is this phenomenon normal? How to trigger a one-time interrupt program without correction?

thank you

  • Hello Jimmy,

    Apologies for the delay here.

    1. Performing error injection requires setting the ECC-IN bit, but TRM states that this bit must remain static before using DDR, which contradicts the need to configure the ECC-IN bit during the injection process. How should I periodically execute this diagnostic measure?

    I am checking on this with the HW expert. But I think, it should be ok even if you change the ECC-IN bit just for the error injection. This is the standard procedure followed by all the customers. 

    2. If an error is only injected during initialization and not corrected in the interrupt program, and triggered during periodic execution, we find that the interrupt can be entered normally when the error is triggered for the first time, but it will continue to enter the interrupt program after being triggered once. Is this phenomenon normal? How to trigger a one-time interrupt program without correction?

    Can you explain a bit more. I did not understand the question properly.

    Regards,

    Nihar Potturu. 

  • Hi Potturu

    Thanks for your reply

    Regarding the second question, we have made such an attempt
    Step 1: Inject ECC errors (not triggered) into DDR specific addresses during the initialization phase.
    Step 2: Accessing DDR during the cycle run phase triggers this error.
    Step 3: Do not correct errors in the interrupt callback function.

    The phenomenon after our testing is as follows:
    After the second step is triggered, the callback function is entered. After the callback function exits, it will immediately re-enter the callback function and cannot execute the normal program.

    Jimmy

  • Hi Jimmy,

    The phenomenon after our testing is as follows:
    After the second step is triggered, the callback function is entered. After the callback function exits, it will immediately re-enter the callback function and cannot execute the normal program.

    Is this being observed for double bit errors? 

    Regards,

    Nihar Potturu. 

  • Hi Potturu

    This phenomenon occurs in both double bit and single bit scenarios。

    Jimmy

  • Hello Jimmy,

    After the second step is triggered, the callback function is entered. After the callback function exits, it will immediately re-enter the callback function and cannot execute the normal program.

    Since, double bit errors are not correctable, the program getting stuck is expected. However, single bit errors are auto corrected, so you should not be seeing this issue if you are clearing the ECC error inside the callback function. Are you calling DDR_ClearECCError API inside the callback?(Attaching screenshot below)

      

    Regards,

    Nihar Potturu. 

  • Hi Jimmy,

      Feedback from internal teams (e.g. DDR-T7) is performed at launch and does not need to be performed on a regular basis.

    Regards,

    Linjun