Tool/software:
Hello,
in my previous design i've had so unstable internal clock that CAN 2.0 on 1Mbit/s was unachievable. my current one based on MSPM0G3519 and i'm tasked with 5Mbit/s CANFD - does TI has results about internal clock stability and it's influence on CANFD operation at high speeds? also could i have stable 2MHz clock on clk_out in very low power mode? thank you
