Problem in enabling IRQ for TMS570LS30336

Hi Firoz,

You can try to clear all pending interrupts in the VIM before enabling the interrupt in the CPSR register.

But first you should figure out which interrupts are pending, before you clear them, just for the case there is a hidden error.

The pending interrupts can be viewed in the INTREQ register they can be cleared with the help of the related module registers.

Furthermore if you use the TI Code Generation Tools there are build in intrinsics which you can use to enable the IRQ / FIQ (e.g. _enable_IRQ() ). These intrinsics are described on page 140 of the C compiler user's guide (http://www.ti.com/lit/ug/spnu151g/spnu151g.pdf#page=140).

Best Regards,

Christian

Firoz,

Your code to enable IRQ in the CPU is correct.

Can you describe with more details what is happening when you enable IRQ?
Where does your code jumps to?

What Christian mentioned is valid. If your VIM is enable, it is possible that you have pending interrupt, so as soon as you enable IRQ, the CPU will start servicing these pending interrupts.

Please provide more details in order to help you fix your problem.

Regards,

Jean-Marc

Hello Jean-Marc,

My code jumps to the NMI handler when i am trying to change the IRQ bit in CPSR (After the third step of IRQ enable logic).

My initial requirement is to enable an Real time interrupt. So I programmed REQENASET[0] to 0x00000004 so as to enable RTI.

Observations:

1. INTREQ0 shows 0x00000001 or 0x00000005 at reset  which means there is an FIQ interrupt of error status module.

2. When I program REQENASET[0] to some phantom interrupt, the code works fine.

Can u be helpful with this info?

Regards

Firoz

Firoz,

Can you tell me the status of ESMSR1, ESMSR2, ESMSR3 at address 0xFFFFF518, 0xFFFFF51C, 0xFFFFF520. These registers are not cleared by a system reset.
They can only be cleared by a power on reset or by software.

According to your last post, you are reading 0x000000001 or 0x00000005 in INTREQ0. When bit 3 is set, this is your RTI compare interrupt 1. This is what you want.

Are you doing the recommended CPU initialization in your boot code?
Because of the dual lock step CPU implementation, it is necessary to insure that both CPU internal registers are initialized to the same value. Failure to do this initialization may create compare error between the 2 cpus.

It will be easier for me if you can share your code, so I can run it and see what is happening.

If you can't share your code, we can try to have a remote session so I can have a look. In which time zone are you?

Thanks and regards,

Jean-Marc

Jean-Marc,

The status of ESMSR1,ESMSR2,ESMSR3 at reset are 0x80000000,0x00000004,0x00000000 respectively. As u suggested, i cleared them in my start up code, but still the same problem re-occurs.

INTREQ0 shows 0x00000005 when i program REQENASET0 to 0x00000008 instead of 0x00000004. But when i program REQENASET0 to 0x00000004, INTREQ0 shows 0x00000001 and jumps NMI handler at third step of IRQ enable logic.

My time zone is GMT+5.30Hr (India standard time).

Please see attached startup code and the below code.

    .global  __clearRegisters_
    .asmfunc

__clearRegisters_:

        mov   r0,   #0x00
        mov   r1,   #0x00
        mov   r2,   #0x00
        mov   r3,   #0x00
        mov   r4,   #0x00
        mov   r5,   #0x00
        mov   r6,   #0x00
        mov   r7,   #0x00
        mov   r8,   #0x00
        mov   r9,   #0x00
        mov   r10,  #0x00
        mov   r11,  #0x00
        mov   r12,  #0x00
        mov   r13,  #0xD1
        msr   cpsr, r13
        mov   r8,   #0x00
        mov   r9,   #0x00
        mov   r10,  #0x00
        mov   r11,  #0x00
        mov   r12,  #0x00
        mov   r13,  #0xD3
        msr   cpsr, r13
        bx    lr

    .endasmfunc




;-------------------------------------------------------------------------------
; Set stack pointer

    .global  __stackPointer_
    .asmfunc

__stackPointer_:

        mov   r0,   #0xD1
        msr   cpsr, r0
        ldr   sp,   fiq

        mov   r0,   #0xD2
        msr   cpsr, r0
        ldr   sp,   irq

        mov   r0,   #0xD7
        msr   cpsr, r0
        ldr   sp,   abort

        mov   r0,   #0xDB
        msr   cpsr, r0
        ldr   sp,   undefined


        mov   r0,   #0xDF
        msr   cpsr, r0
        ldr   sp,   user

           mov   r0,   #0xD3
        msr   cpsr, r0
        ldr   sp,   svc


        bx    lr

user:      .word 0x08000000
svc:       .word 0x08000400
fiq:       .word 0x08000800
irq:       .word 0x08000A00
abort:     .word 0x08000D00
undefined: .word 0x08000E00

    .endasmfunc

Thanks & Regards

Firoz

Firoz,

let me add some comments on the ESM module and your CPU register initialization code.

ESM:
The ESM on your device does have more status register than mentioned by Jean-Marc so far, because error group 1 was extended to 64 entries. Thus there is a 4th register set ESMxxx4 to extend ESMxxx1. For ESM group2, which always will do a NMI in case one or more errors a flagged for this group, there is a shadow register ESMSSR2 for the 'normal' status register ESMSR2. Purpose of this Shadow register is to flag the error status after  a reset has occurred, because ESMSR2 gets reset by a 'normal' reset. This is different compared to the other status register. I'd recommend to have a look to the ESM register descriptions in the TRM (spnu499) having a special focus on their reset behavior shown below the register bit fields.

CPU register:
The device runs in lock-step where output signals of both CPUs are permanently compared by the CCM module. The CPU internal registers R0-R15 are not getting reset, therefore you must initialize them at the beginning of your device startup to avoid CCM errors getting flagged and therefore causing a NMI (see ESM grp2, ch2). In your __clearRegisters_ function you are already doing such initialization, but there are more register inside the CPU which you need to initialize. Think about the banked registers for the other operating modes (may be not used in your application); like you do for the stack set up.

In addition there are also register inside the FPU you need to initialize in case you enable the FPU, e.g. by a code like

 .if (isVfpEnabled == 1)
        fmdrr d0,        r1,     r1
        fmdrr d1,        r1,     r1
        fmdrr d2,        r1,     r1
        fmdrr d3,        r1,     r1
        fmdrr d4,        r1,     r1
        fmdrr d5,        r1,     r1
        fmdrr d6,        r1,     r1
        fmdrr d7,        r1,     r1
        fmdrr d8,        r1,     r1
        fmdrr d9,        r1,     r1
        fmdrr d10,       r1,     r1
        fmdrr d11,       r1,     r1
        fmdrr d12,       r1,     r1
        fmdrr d13,       r1,     r1
        fmdrr d14,       r1,     r1
        fmdrr d15,       r1,     r1
    .endif

And just to get complete, there are 4 branch and link register inside the CPU you need to in initialize by software too.
This can be done by issuing 4 'bl' instructions after the formerly mentioned register got initialized; e.g.

        bl    next1
next1
        bl    next2
next2
        bl    next3
next3
        bl    next4
next4
        bx    r0

I hope this helps.

Kind Regards,
    Rainer