AM2434: OSPI READ COMMAND first bit half-level question.

Update:

With default OSPI configuration. "Protocol Enable Configuration"->"Dummy Clocks(READ)" = 25, but flash chip dummy register =24. But when i modefiy them to same such as 24 or 25 or 8, failed as read incorrect value from flash.

So why the host dummy cycle need be larger than slave?

Hi,

I am supposing you are on a custom board.

If yes, then can you go ahead and run the OSPI Flash diagnostics example.

This way it would give some value for dummy clocks command and dummy clocks read.

I know that the value is already populated onto the SysConfig for the flash part S28HL512T, but I would appreciate if you could run the diagnostics and share the logs as well.

Please set the dummy clocks read and dummy clocks command from the logs.

Regards,

Vaibhav

Hi Vaibhav,

The key question is:

How to configure dummy cycle for OSPI controller and device/flash. From test result, on controller side need to be 1 more cycle than device/flash side. 

The default sysconfig of OSPI example also set to this pattern, the reason and the basis? 

Vaibhav Kumar said:

Please set the dummy clocks read and dummy clocks command from the logs.

This modthed doesn't work, I have already tried on S28HS512T/S28HL512T/MX25LM256.

Read out json config as show below:

{

"flashSize": 67108864,
"flashPageSize": 256,
"flashManfId": "0x34",
"flashDeviceId": "0x5A1A",
"flashBlockSize": 262144,
"flashSectorSize": 4096,
"cmdBlockErase3B": "0xDC",
"cmdBlockErase4B": "0xDC",
"cmdSectorErase3B": "0x21",
"cmdSectorErase4B": "0x21",
"protos": {
"p111": {
"isDtr": false,
"cmdRd": "0x03",
"cmdWr": "0x02",
"modeClksCmd": 0,
"modeClksRd": 0,
"dummyClksCmd": 0,
"dummyClksRd": 0,
"enableType": "0",
"enableSeq": "0x00",
"dummyCfg": null,
"protoCfg": null,
"strDtrCfg": null
},
"p112": null,
"p114": null,
"p118": null,
"p444s": null,
"p444d": null,
"p888s": null,
"p888d": {
"isDtr": true,
"cmdRd": "0xEE",
"cmdWr": "0x12",
"modeClksCmd": 0,
"modeClksRd": 0,
"dummyClksCmd": 4,
"dummyClksRd": 24,
"enableType": "0",
"enableSeq": "0x00",
"dummyCfg": {
"isAddrReg": true,
"cmdRegRd":"0x65",
"cmdRegWr":"0x71",
"cfgReg":"0x00800003",
"shift":0,
"mask":"0x03",
"bitP":11
},
"protoCfg": {
"isAddrReg": true,
"cmdRegRd": "0x65",
"cmdRegWr": "0x71",
"cfgReg": "0x00800006",
"shift": 0,
"mask": "0x00",
"bitP": 0
},
"strDtrCfg": {
"isAddrReg": true,
"cmdRegRd": "0x65",
"cmdRegWr": "0x71",
"cfgReg": "0x00800006",
"shift": 1,
"mask": "0x00",
"bitP": 1
}
},
"pCustom": {
"fxn": null
}
},
"addrByteSupport": "1",
"fourByteAddrEnSeq": "0xA0",
"cmdExtType": "REPEAT",
"resetType": "0x10",
"deviceBusyType": "1",
"cmdWren": "0x06",
"cmdRdsr": "0x05",
"srWip": 0,
"srWel": 1,
"cmdChipErase": "0xC7",
"rdIdSettings": {
"cmd": "0x9F",
"numBytes": 5,
"dummy4": 0,
"dummy8": 0
},
"xspiWipRdCmd": "0x65",
"xspiWipReg": "0x00800000",
"xspiWipBit": 0,
"flashDeviceBusyTimeout": 256000000,
"flashPageProgTimeout": 512
}

Hi,

The values set on the SysConfig front, is tested out on the TI EVM and works for the same.

Is there any functional blockage due to the values being set currently on your custom board?

Regards,

Vaibhav

Hi Vaibhav,

It is functional,

#1. But the waveform is abnormal on the first data bit of reading. How to interpret the waveform of middle level.

#2. 24/25 is for 200MHz, it is too larger and not necessary for 33.5MHz, waste cycles and lead low throughput.

#3. Verified 5(flash)/6(soc) dummy cycle with 33.5MHz, it passed data write/read test.

Hi Tony,

I would need to run this by on my TI EVM.

Can you let me know from the highlighted section below, when to look out for this behaviour?

Is it right before a read/write transaction begins or somewhere else?

Regards,

Vaibhav 

First bit of data stage of each Read transaction.

Can capture it during OSPI booting also.

liang luo said:

Corresponding to the following mark .

As show in this picture, if the first readout byte equal to 0xff, you can reproduce this behaviour on all DQs pins

Hi Vaibhav, any update? Same issue can be reproduce on EVM board.

Hi,

Tony Tang said:

The default sysconfig of OSPI example also set to this pattern, the reason and the basis? 

Please read through this: https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1474635/processor-sdk-am64x-ospi-dummy-cyle-settings-why-4/5678646#5678646

and this: https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1474635/processor-sdk-am64x-ospi-dummy-cyle-settings-why-4/5678663#5678663

Regards,
Vaibhav

Hi Vaibhav,

You thread told how to select dummy cycle number according to ospi clock frequency running. 

But my question is:  

#1. Why need to configure dummy cycle on controller side to be 1 more cycle than device/flash side. otherwise access fail.

#2. With #1 get the wave form first data bit in middle level.

Hi Tony,

Tony Tang said:

24/25 is for 200MHz, it is too larger and not necessary for 33.5MHz,

What is the clock frequency and clock divider set by the customer? Please also tell me if:

1. DMA is enabled in OSPI section or not.
2. What about the Phy enabled option.

Tony Tang said:

#1. Why need to configure dummy cycle on controller side to be 1 more cycle than device/flash side. otherwise access fail.

I have checked this with the SW team. Ideally it should have been the value assume x, which is mentioned on the flash datasheet.

Due to other delays on the TI EVM board and while the board bringup was happening, we set a value which has a delta of 1 from what is mentioned in the flash datasheet.

Tony Tang said:

#2. With #1 get the wave form first data bit in middle level.

I will get this waveform after I have the DQS line probed, currently I have all the data lines, chip select and the clock probed. Once, I have the waveform I will share how the first bit is captured and show the behaviour of CS, CLK, D0...D7 and DQS lines. From this point onwards, we can continue our discussion and plan for improvements if any.

Looking forward to your response.

Regards,

Vaibhav

Hi Vaibhav,

Vaibhav Kumar said:

What is the clock frequency and clock divider set by the customer? Please also tell me if:

We know how to set, just want to let BU know the default sysconfig value is not reasonable. 

Vaibhav Kumar said:

Due to other delays on the TI EVM board and while the board bringup was happening, we set a value which has a delta of 1 from what is mentioned in the flash datasheet.

Still not understand why, if due to board delay, should minus 1 other than plus 1 cycle vs. flash datasheet mentioned. 

And if it is the rule, should highlight it somewhere.

Vaibhav Kumar said:

I will get this waveform after I have the DQS line probed, currently I have all the data lines, chip select and the clock probed.

Are you working for other issue, for this issue, capture one data bit is enough, and just check the first bit edge, of cause need it be 1 other than 0.

Hi Tony,

Thanks for your patience.

Tony Tang said:

Still not understand why, if due to board delay, should minus 1 other than plus 1 cycle vs. flash datasheet mentioned. 

And if it is the rule, should highlight it somewhere.

I will check with the Software team on how we can improve this offering and make it easy for the customer to understand.

Tony Tang said:

Are you working for other issue, for this issue, capture one data bit is enough, and just check the first bit edge, of cause need it be 1 other than 0.

There is always a parallel issue which I am working on, so I am juggling between threads. That should not be a concern for me to send you a waveform, but the following waveform would be without DQS line probed, it will show you the CS, CLK, and all the 8 data lines D0,....D7.

Please find it here:

https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/908/memcpy_5F00_128bytes_5F00_8d_5F00_8d_5F00_8d.sal

How to view the waveform?

To view the waveform simply head over to this website and download the Logic 2 software: https://www.saleae.com/pages/downloads

Once downloaded, you can save the attached waveforms which have an extension of .sal and then simply click on it. It will automatically open the Logic 2 software and show the waveform.

Regards,

Vaibhav

Vaibhav Kumar said:

There is always a parallel issue which I am working on, so I am juggling between threads. That should not be a concern for me to send you a waveform, but the following waveform would be without DQS line probed, it will show you the CS, CLK, and all the 8 data lines D0,....D7.

Please find it here:

memcpy_128bytes_8d_8d_8d.sal

Hi Vaibhav, 

Logic analyzer is not suitable to catch half-level, it only has two values 0/1. Oscilloscope is ok.

liang luo said:

Logic analyzer is not suitable to catch half-level, it only has two values 0/1. Oscilloscope is ok.

 I need to see if I can get an oscilloscope real quick and capture the waveform.

Allow me several business days. I will provide an update once I have progress on this.

Will it be okay, if I capture the waveform on 1S-1S-1S mode?

Because getting all 8 data lines will be challenging task especially with Oscilloscope.

Regards,

Vaibhav

Vaibhav Kumar said:

Because getting all 8 data lines will be challenging task especially with Oscilloscope.

Why do you think need to capture all 8 data lines? we stated clearly just check the first bit of any data line waveform.

Hi Vaibhav,

Is there update about the waveform?

I am measuring the waveforms at the moment and will update in sometime.

Thanks for the gentle reminder on this.

Hi,

I am seeing the following with Analog waveform option chosen with logic analyzer.

Regards,

Vaibhav

Vaihbav,

It is not the point we want to check. 

#1. Our question is the first bit of READ data, not the first bit of read command. 

#2. The analog waveform of logic analyzer sample rate is not enough, doesn't provide valuable information.

#3. Can you find a oscilloscope? 

Tony Tang said:

#3. Can you find a oscilloscope? 

It is currently in use by another team for debugging another customer issue.

I will get hands on it in sometime and check the waveforms.

Hi,

This is what I see when I read lets suppose 128 bytes using OSPI_readDirect and the probing happens exactly when memcpy is executed.

Pretty sure its the data bits seen on the waveform as for sending command and address bytes, D0 line sends the bit 0.

Regards,

Vaibhav

Vaibhav Kumar said:

probing happens exactly when memcpy is executed.

Vaibhav Kumar said:

Pretty sure its the data bits seen on the waveform as for sending command and address bytes, D0 line sends the bit 0.

If so, it is command and address stage, not the data read back from flash stage.

We need to see the first Data bit edge of read data. not command and address stage data pin waveform.

It is better to probe DQS together, then can know when is the first read data bit.

I have all the lines taken out/probed, except DQS, once I have DQS out as well in sometime, then I can go ahead and capture both D0 and DQS so that its known when the first bit is captured.

Accordingly I will send you a photo of the same once I have done it.

Thanks for your patience.

Sincerely,

Vaibhav

There are many resistor stubs on DQS net, it is not hard to probe it on EVM. customer did it very easy. Is there a schedule?

Again, not need to probe all data pin. trigger with DQS to capture any one data pin as long as the data is FF, then the first bit is HIGH, can see middle level signal.

Hi Tony,

I can provide an update within this week.

Regards,

Vaibhav

Hi,

I have got the DQS and Data line D0 probed and saw the signal as follows:

I have read 128 bytes.

You see the behaviour when you are reading how many bytes? Also, I am assuming you have Phy enabled as well, because then only the DQS line will be effective else its not used.

Regards,

Vaibhav

The waveform is somewhat distorted, I suggest turn off phy mode to slow down the frequency.

DQS is valid even if phy mode turn off. Your DQS waveform seem some problems, not sure it's a wrong pin or oscilloscope problem

Vaibhav Kumar said:

I am assuming you have Phy enabled as well, because then only the DQS line will be effective else its not used.

Hi,

Thanks for your patience.

liang luo said:

The waveform is somewhat distorted, I suggest turn off phy mode to slow down the frequency.

DQS is valid even if phy mode turn off.

Well when Phy mode is not turned on in SysConfig, DQS should be not effective at all.

DQS is only used when we enable Phy, so combining DQS with reading while phy is not enabled, does not makes sense.

Infact reset value of DQS enable field in one of the OSPI registers starting from FC40000 is 0, and not 1. It is set to 1, when we call the API OSPI_phyTuneDDR or OSPI_phyTuneSDR

Regards,

Vaibhav