MSPM0G3507: ADC Ping Pong Example gives MEMRESx overflow out of the box

Hi Kai,

Can you change the DMA trigger to an earlier value? Try MEMRES6 is loaded, instead of MEMRES11. Since the ADC is in repeat mode, it will keep sampling forever and with FIFOs it will use all the MEMRES registers and write to the next data, this can overwrite previous values if the DMA did not read the data, which causes the overflow interrupt.

I'll look into code example to balance it for the ADCs input 

Regards,
Luke

Setting the dma trigger to mem10 already results in an underflow. The sample time is 10us, so it makes sense to me. Additionally an overflow is set, which makes me questioning the trustworthyness of the overflow.

Hi Kai,

Can you check when the underflow and overflows are getting triggered. For example, is the overflow on the first DMA trigger and the underflow on the second?

Regards,
Luke

Hi,
1)with dma trigger on mem10:
Underflow is set when first dma interrupt happens
Overflow is set when second dma interrupt happens

2)with dma trigger on mem11

Overflow is set when second dma interrupt happens

Code 

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#include "ti_msp_dl_config.h"

#define ADC_SAMPLE_SIZE (64)

/* When FIFO is enabled 2 samples are compacted in a single word */
#define ADC_FIFO_SAMPLES (ADC_SAMPLE_SIZE / 2)

uint16_t gADCSamplesPing[ADC_SAMPLE_SIZE];
uint16_t gADCSamplesPong[ADC_SAMPLE_SIZE];

volatile bool gCheckADC;
volatile bool gPing;
volatile bool gOverflow;
volatile bool gUnderflow;
volatile uint32_t gOverflowCounter;
volatile uint32_t gUnderflowCounter;


int main(void) {
  gOverflow = false;
  gUnderflow = false;
  gOverflowCounter = 0U;
  gUnderflowCounter = 0U;
  gPing = true;

  SYSCFG_DL_init();

  /* Configure DMA source, destination and size */
  DL_DMA_setSrcAddr(DMA, DMA_CH0_CHAN_ID, (uint32_t)DL_ADC12_getFIFOAddress(ADC12_0_INST));
  DL_DMA_setDestAddr(DMA, DMA_CH0_CHAN_ID, (uint32_t)&gADCSamplesPing[0]);
  DL_DMA_setTransferSize(DMA, DMA_CH0_CHAN_ID, ADC_FIFO_SAMPLES);
  DL_DMA_enableChannel(DMA, DMA_CH0_CHAN_ID);

  /* Setup interrupts on device */
  NVIC_EnableIRQ(ADC12_0_INST_INT_IRQN);

  gCheckADC = false;

  /* The ADC is configured for Repeat Single Conversion,
   * so the ADC will continue until DL_ADC12_disableConversions() is called */
  DL_ADC12_startConversion(ADC12_0_INST);

  while (1) {

    while (false == gCheckADC) {
      __WFE();
    }
    /* Breakpoint to check the buffers and watch the Ping Pong operation.
     * The data will be alternating between each buffer.
     */
    //__BKPT(0);

    /* Switch to send ADC Results to Pong Buffer */
    if (gPing) {

      DL_DMA_setDestAddr(DMA, DMA_CH0_CHAN_ID, (uint32_t)&gADCSamplesPong[0]);
      DL_DMA_setTransferSize(DMA, DMA_CH0_CHAN_ID, ADC_FIFO_SAMPLES);
      DL_DMA_enableChannel(DMA, DMA_CH0_CHAN_ID);
      DL_ADC12_enableDMA(ADC12_0_INST);

      gPing = false;
    }
    /* Switch to send ADC Results to Ping Buffer */
    else {

      DL_DMA_setDestAddr(DMA, DMA_CH0_CHAN_ID, (uint32_t)&gADCSamplesPing[0]);
      DL_DMA_setTransferSize(DMA, DMA_CH0_CHAN_ID, ADC_FIFO_SAMPLES);
      DL_DMA_enableChannel(DMA, DMA_CH0_CHAN_ID);
      DL_ADC12_enableDMA(ADC12_0_INST);

      gPing = true;
    }
  }

  gCheckADC = false;
}

void ADC12_0_INST_IRQHandler(void) {
  gOverflow = gOverflow || DL_ADC12_getRawInterruptStatus(ADC12_0_INST,DL_ADC12_INTERRUPT_OVERFLOW);
  gUnderflow = gUnderflow || DL_ADC12_getRawInterruptStatus(ADC12_0_INST,DL_ADC12_INTERRUPT_UNDERFLOW);
  if(!gOverflow){
    gOverflowCounter++;
  }
  if(!gUnderflow){
    gUnderflowCounter++;
  }
  switch (DL_ADC12_getPendingInterrupt(ADC12_0_INST)) {
  case DL_ADC12_IIDX_DMA_DONE:
    gCheckADC = true;
    break;
  default:
    break;
  }
}

Thanks Kai, I'll see if I can replicate this on my end and investigate the conditions further. 

Do you need the ADC samples in continuous repeat mode, and you want to verify you don't miss any samples?

Luke Ledbetter said:

Do you need the ADC samples in continuous repeat mode, and you want to verify you don't miss any samples?

Exactly, I bascially want to do whats done in the example, but I've noticed the overflow flag is set for my setup. Therefore I checked the example and discovered the same behavior.

Thanks!

Hi Kai,

Do you have a target sampling rate?

I am able to replicate the same with the current 10us, and adjusting the parameters of Sampling Speed, DMA Trigger source (which MEMRES is loaded) and the early interrupt thresholds change the behavior of the the overflow and underflow conditions.

Currently I am investigating configurations for avoiding the overflow condition.

Regards,
Luke

Hi,
this is what I have in my actual project (250ns on 4 channels, but with hw averaging, therefore 125ns):
hw averaging ist not mandatory.


If you can find the root cause of the overflow it would be nice to understand what causes it.

Thanks

Hi,
I see, the problem in the demo is that 32 isn't a multiple of 12.

Two other questions:

Wrt my problem, I couldn't find any documentation for the difference of the "valid trigger" and "trigger".
1) Do you know where I can find that?

For my actual code I noticed that as soon as I turn on compiler optimizations, the overflow flag is not set during continous sampling. It is set though, when I start transmitting data in parallel (via dma and spi).
2)Is there a best practice how you can approach such a change in load. E.g. change the memresX interrupt for the adc dma, or trigger the renabling of the dma earlier?

Thanks!

Hi Kai,

A valid trigger is instance of the trigger source, for example if you're triggering from an event or software, another SW call or Event will be a "valid" trigger, otherwise it will move to the next channel as soon as the previous is finished.

There are early interrupts you can have the DMA set to do, so the interrupt will fire before all the transfers have finished. For race conditions it is usually easier to handle if you guarantee one doesn't lap the other. So if you have the last ADC channel wait for the DMA to finish then restart the ADC sampling you'd know that the ADC won't overflow. The problem is that will restrict your total throughput as you will be limited by the DMA finish.

Is your SPI transaction predictable, ie: we're the controller or the SPI request will happen every X amount of time?

If the SPI is predictable then you can adjust your settings to compensate for the additional handling.

Regards,
Luke