This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

AM2632: GPIO interrupt

Part Number: AM2632
Other Parts Discussed in Thread: SYSCONFIG

Tool/software:

Dear TI Support Team,

I hope this email finds you well.

I am currently working on configuring a GPIO interrupt triggered by a rising edge. In the existing example code, the implementation uses GPIO-bank-INTR. However, I need to configure a single GPIO pin to trigger its own dedicated interrupt instead of sharing a bank-level interrupt.

Could you kindly clarify the following questions?

  1. How should I configure a single GPIO to map to a unique interrupt (instead of a bank)?

  2. In SysConfig, there is a "GPIO INT XBAR" section. I would like to understand:

    • How do the XBAR Output and XBar Instance parameters correspond to each other?

  3. Could you provide guidance on the interrupt configuration steps in the code (e.g., registering ISRs, enabling interrupts, etc.)?

  4. I have also looked at the link description below and I would like to know how gPepiaPinIntrNum and gPepiaBankIntrNum are configured and their corresponding relationship with syscfg                          software-dl.ti.com/.../DRIVERS_GPIO_PAGE.html

    void gpio_bank_interrupt_init(void)
    {
        int32_t         retVal;
        uint32_t        pinNum = gGpioPinNum, bankNum;
        HwiP_Params     hwiPrms;
     
        bankNum = GPIO_GET_BANK_INDEX(pinNum);
     
        /* Interrupt setup */
        GPIO_setDirMode(gGpioBaseAddr, pinNum, GPIO_DIRECTION_INPUT);
        GPIO_setTrigType(gGpioBaseAddr, pinNum, GPIO_TRIG_TYPE_RISE_EDGE);
        GPIO_bankIntrEnable(gGpioBaseAddr, bankNum);
     
        /* Register bank interrupt */
        HwiP_Params_init(&hwiPrms);
        hwiPrms.intNum = gGpioBankIntrNum;
        hwiPrms.callback = &GPIO_bankIsrFxn;
        hwiPrms.args = (void *) pinNum;
        retVal = HwiP_construct(&gGpioHwiObject, &hwiPrms);
        if(SystemP_SUCCESS != retVal)
        {
            DebugP_assert(FALSE);
        }
    }
    
    void gpio_pin_interrupt_init(void)
    {
        int32_t         retVal;
        uint32_t        pinNum = gGpioPinNum, bankNum;
        HwiP_Params     hwiPrms;
     
        bankNum = GPIO_GET_BANK_INDEX(pinNum);
     
        /* Interrupt setup */
        GPIO_setDirMode(gGpioBaseAddr, pinNum, GPIO_DIRECTION_INPUT);
        GPIO_setTrigType(gGpioBaseAddr, pinNum, GPIO_TRIG_TYPE_RISE_EDGE);
        GPIO_bankIntrEnable(gGpioBaseAddr, bankNum);
     
        /* Register pin interrupt */
        HwiP_Params_init(&hwiPrms);
        hwiPrms.intNum = gGpioPinIntrNum;
        hwiPrms.callback = &GPIO_pinIsrFxn;
        hwiPrms.args = (void *) pinNum;
        retVal = HwiP_construct(&gGpioHwiObject, &hwiPrms);
        if(SystemP_SUCCESS != retVal)
        {
            DebugP_assert(FALSE);
        }
    }

My requirement is r5fss1-0, PR0_PRU0_GPIO4,pin interrupt。

Please provide me with specific syscfg and gPepiaPinIntrNum。

Thank you for your time and support!

Best regards,

zx

  • Hi all:

    Can anyone answer my question? Urgent use

    Best regards

    zx

  • Hello zx,

    However, I need to configure a single GPIO pin to trigger its own dedicated interrupt instead of sharing a bank-level interrupt.
    How should I configure a single GPIO to map to a unique interrupt (instead of a bank)?

    Sure this can be done using the GPIO INT XBAR. I'll walk through the details for you.

    In SysConfig, there is a "GPIO INT XBAR" section. I would like to understand:

    • How do the XBAR Output and XBar Instance parameters correspond to each other?

    The XBar Instance determines where you are routing the GPIO INT to - it can be routed to the ICSSM XBAR, EDMA Trigger, TimeSync XBAR, or any of VIM[0:3]. In this case, to finish the example configuration I'd need to know the destination but for now I will assume a VIM interrupt going to the R5FSS1-0 core is what you need.

    The XBAR Output refers to what the XBAR will output to the destination it is being routed to, and it can be any of the GPIO mux options or GPIO bank interrupts.

    The GPIO INT XBAR has detailed covered as part of 10.3.1 INTRTR Overview and 10.3.2.3 GPIO XBAR INTRTR0.

    Could you provide guidance on the interrupt configuration steps in the code (e.g., registering ISRs, enabling interrupts, etc.)?

    You'd need to instantiate the GPIO associated with the desired pin - in this case it seems to be ball K16 which is equivalent to GPIO92 (this info comes from the device datasheet0. Then you can configure GPIO INT to use XBAR with the corresponding Mux option to select this I/O.

    From there, to route it to the R5FSS1-0 Core VIM, you'd need to route it through one of the four interrupt inputs the VIM will accept which is one of R5FSS1_CORE0_INTR_GPIO_INTRXBAR_OUT_22 through R5FSS1_CORE0_INTR_GPIO_INTRXBAR_OUT_25. These come out via VIM2 which you can see with Figure 10-4. GPIO XBAR Interrupt Router Integration Diagram where GPIO Interrupt XBAR signals [25:22] are routing to VIM2.

    So you'd be looking at this SysConfig:

    I have also looked at the link description below and I would like to know how gPepiaPinIntrNum and gPepiaBankIntrNum are configured and their corresponding relationship with syscfg                          software-dl.ti.com/.../DRIVERS_GPIO_PAGE.html

    I am not finding the variable names you mentioned in that link, can you check that you have provided the right one?

    Best Regards,

    Ralph Jacobi

  • Hi Ralph:

     Thanks for your reply.

    Is the intrNum that needs to be specified for initialization code corresponding to this, as shown in the following figure

        /* Register pin interrupt */
        HwiP_Params_init(&hwiPrms);
        hwiPrms.intNum   = CSLR_R5FSS1_CORE0_INTR_GPIO_INTRXBAR_OUT_22;

    Best regards

    zx

  • Hi zx,

    Looking through the CSLR files, yes that would be correct.

    CSLR_R5FSS1_CORE0_INTR_GPIO_INTRXBAR_OUT_22 would correspond with GPIO_INT_XBAR_VIM_MODULE2_0 and CSLR_R5FSS1_CORE0_INTR_GPIO_INTRXBAR_OUT_25 would correspond with GPIO_INT_XBAR_VIM_MODULE2_3.

    Best Regards,

    Ralph Jacobi