MCU-PLUS-SDK-AM243X: How to activate TCP over shared RAM between two cores.

Hello Eli,

The default way we enable to do inter-processor communication (IPC) is with IPC_Notify & IPC_RPMsg.

Refer to
https://software-dl.ti.com/mcu-plus-sdk/esd/AM243X/10_00_00_20/exports/docs/api_guide_am243x/IPC_GUIDE.html
https://software-dl.ti.com/mcu-plus-sdk/esd/AM243X/10_00_00_20/exports/docs/api_guide_am243x/DRIVERS_IPC_NOTIFY_PAGE.html
https://software-dl.ti.com/mcu-plus-sdk/esd/AM243X/10_00_00_20/exports/docs/api_guide_am243x/DRIVERS_IPC_RPMESSAGE_PAGE.html
https://software-dl.ti.com/mcu-plus-sdk/esd/AM243X/10_00_00_20/exports/docs/api_guide_am243x/EXAMPLES_DRIVERS_IPC_NOTIFY_ECHO.html
https://software-dl.ti.com/mcu-plus-sdk/esd/AM243X/10_00_00_20/exports/docs/api_guide_am243x/EXAMPLES_DRIVERS_IPC_RPMESSAGE_ECHO.html

I am not sure if we have any examples of defining a TCP server to communicate between cores, instead of to communicate over the Ethernet interface. I am reassigning your thread to another team member to comment.

Regards,

Nick

Hi Nick,

Thanks,

Regards,

Eli

Hi Eli, unfortunately we don't have an example that shows how to set up a TCP server/client on two cores which communicates over MSRAM or TCM

From code inspection, if you want to bypass the PHY and use shared RAM for communication, I believe you need to modify the network interface layer of the LwIP stack (lwipif) to RD/WR packets directly from/to the shared RAM. This seems to be a non-trivial task. 

I would suggest letting us know if you face any specific issue while implementing it, or if you have any question(s) w.r.t our LwIP, then we can take those questions / issues in separate E2E threads

Thank you,

Paula

Hi Paula,

Can you please advice on how to configure the enet via syscfg for core-1.

Thanks,

Best Regards,

Eli

Hi Paula,

Since I'm trying to communicate via the sharaed ram , maybe I can directely use tcp_init() but I still prefer to do it the correct way via the syscfg. 

I'm looking for a particular configuration that will allow me to bypass the dma and the mdio.

Thanks,

Best Regards,

Eli

Hi Paula,

Is there a "virtual" ethernet driver on shared ram in the lwip package supported by TI ?

Thanks,

Best Regards,

Eli

Hi Eli, please open a new E2E so it would be easier to send it to correct expert. You can refer this thread from the new one if you think it could help to give context

thank you,

Paula

Hello Eli,

What exactly are you trying to accomplish with your IPC? Is there a specific reason that IPC Notify, IPC RPMsg, or a shared memory implementation that uses those for notification would not fit your system?

Please keep in mind that we are not able to support questions about modifying TI drivers, as we have not validated that ourselves. So if you really want to dig into modifying the enet driver, you are going to have to do that mostly on your own. We will be limited in the support that we can offer.

Regards,

Nick

Hi Nick,

I'm trying to activate LwIP with the TCP protocol on both cores without using drivers. I would like all packets to be written to and read from shared RAM.

I'm having difficulty getting tcpip_init() to work with FreeRTOS.

Could you please guide me on how to do it?

Thanks.

Best regards,
Eli

Hello Eli,

My understanding is that LwIP was designed for intra-processor communication, over Ethernet (for example, if you have an AM243x and an AM263x and they are communicating over Ethernet). It was not designed for inter-processor communication, between cores inside of the same processor.

Can I get you to respond to my previous question?

"What exactly are you trying to accomplish with your IPC? Is there a specific reason that IPC Notify, IPC RPMsg, or a shared memory implementation that uses those for notification would not fit your system?"

If you give us more information, we can give you more guidance on IPC methods we would suggest for your design.

* how much data are you trying to send at a time?
* Do you have latency requirements for how long it takes data to get from one core to another?
* Do you have throughput requirements?
* etc

Regards,

Nick

Hi Nick,

The idea is to use a standard, reliable protocol as an IPC between cores.

We already have a TCP/IP-based IPC between cores in our AM57xx project.

My task is to implement the low-level layer for LwIP in our AM243x project.

I thought perhaps someone from TI could guide me on the best way to do this, based on the TCP server example.

This requires bypassing all hardware and using only the LwIP stack in RAM.

Thanks,
Best regards,
Eli

Hi Nick,

About your questions:

* How much data are you trying to send at a time?
* Do you have latency requirements for how long it takes data to get from one core to another?
* Do you have throughput requirements?

It's not a hard real time IPC. 

I think that we send about 100bytes every 16msec

Latency should not ecxeed 1,2 msecs

Througput is ~625 bytes/sec

Thanks,

Best Regards,

Eli

Hello Eli,

I would encourage you to evaluate RPMsg first in that case. Your development flow will be much easier, and we will actually be able to answer questions and provide support if you need it. RPMsg is standardized (if you ever need to add Linux to your design and move to an AM64x, RPMsg and mailboxes are actually the default communication method used between Linux and the R5F / M4 cores).

You can find the default ipc_rpmsg_echo example in your MCU+ SDK here:
https://github.com/TexasInstruments/mcupsdk-core-k3/tree/k3_main/examples/drivers/ipc/ipc_rpmsg_echo

Regards,

Nick

Hi Nick,

Is there a way via syscfg to add another ip interface ?

Thanks,

Best Regards,

Eli