Tool/software:
Hey.
I am trying to synchronize some control logic in my code to the CCD1 event of TIMA1.
So I am running a function where I enable this interrupt:
static inline void load_test(uint32_t load_value)
{
GPIOB->DOUTTGL31_0 = DL_GPIO_PIN_3;
// insert control logic here.
// Clear any previous IRQ, then enable.
TIMA1->CPU_INT.IIDX;
TIMA1->CPU_INT.IMASK = DL_TIMER_EVENT_CC1_DN_EVENT;
GPIOB->DOUTTGL31_0 = DL_GPIO_PIN_3;
}
Then in the ISR I disable the interrupt again:
void TIMA1_IRQHandler()
{
GPIOB->DOUTTGL31_0 = DL_GPIO_PIN_17;
// Disable this IRQ
TIMA1->CPU_INT.IIDX;
TIMA1->CPU_INT.IMASK = 0;
// Insert some control logic here.
GPIOB->DOUTTGL31_0 = DL_GPIO_PIN_17;
}
The NVIC is enabled in the main code:
NVIC_EnableIRQ(TIMA1_INT_IRQn);
The issue now is, that I can see that this interrupt is fired immediately when it is enabled - it does not wait for the next CCD1 event.
I dont quite understand why - my thinking is it could be pending interrupts, but I assume they are cleared by reading the IIDX register.
I dont quite understand why - my thinking is it could be pending interrupts, but I assume they are cleared by reading the IIDX register.
I tried the same code, but instead enabling/disabling the NVIC, but this provided the same result.
What am I missing?
