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MIBSPI Query

Bindu Tanguturi
Expert 1180 points

Other Parts Discussed in Thread: HALCOGEN

Hi Gregor,

I am back to SPI module. I will put my question again.

As i mentioned in the previous posts, i am using TMS570 kit which is interacting with the HI3593 and HI6121 through the SPI. I have to write the SPI drivers. I have written the SPI code in compatibility mode. I tested using oscilloscope and looks working fine.

My idea is to use the Multi buffer RAM in the compatibility mode. I need your guidence for this.

My device requires the following sequence. [ Send Opcode (8bit for writing or reading), Send data or receive data). So my plan is to initializae the transmitt buffer with opcode followed by the data to be transmitted and receive buffer to hold the data

Ex :  TX RAM : 0x0000 - Opcode [for sending 32 bytes of data], 0x0002h - 0x0040- 32 byte Data, 0x0042 - Opcode[for Reading 32 bytes of data], RX RAM : 0x0200 - 0x0240 -32 bytes Data available for reading

The intention is to reduce the CPU overhead in sending/receiving  the data by SPI. So main program places the data to be transmitted in Tx RAM and data to be received in Rx RAM. The sedning/receiving overhaed has to be taken care by SPI module. Please let me know is it possible to setup to like above. And provide me guidence for the same.


  • 0
    TI__Genius 14205 points

    Hi Bindu,

    Yes it is very much posible to configure mibSPI for your need.

    What do you mean by " main program places the data to be received in Rx RAM", are you expecting MibSPI to do receive data check? MIBSPI puts the received data from the external Slave in to the RXRAM, user software should read the data from RXRAM once the TG Complete interrupt is generated.( i.e complete data frame is received in your case after 32 bytes of data).

    Suggesions from my side considering your case, I assumed data width as 8bits and TX & RX happens on same slave one after other. 

    Option 1 - Regular MIBSPI mode

    1) Configure 2 Transfer groups - TG0 for TX and TG1 for RX
    2) TG0 length ( 1 + 32 bytes --- opcode + data) offset 0x0 to 0x7C - (1 byte of data uses 1 buffer,  Each buffer is 32 bit boundary - 16bit control field + 16bit data field) ( if slave supports 16 bit then TG length will reduce)
    3) TG1 length ( 1 + 32 bytes --- opcode + data) offset 0x80 write the data
    4) Fill the opcode + TX data in to TG0 buffers
    5) Fill the opcode to TG1 buffer ( offset 0x80)
    4) You can configure TG's to external triggers or Software trigger always( just enable TG it will tigger the transfer)
    5) Trigger TG0, wait for TG complete interrupt to data transfer complete. In the ISR you can fill the next data or just service and come out it's up to user.
    6) Trigger TG1, wait for TG complete interrupt to data transfer complete. In the ISR you read the received data 32 bytes from offset 0x84..  Each buffer will hold 1 data byte assuming data width as 8-bit

    Option 2 - Using DMA and Compatibility mode SPI

    Option 3 - Using DMA and MIBSPI

    Like Option 1 but with 1 buffer you can transmit 32bytes of data - Refer example in HALCoGen - which can be found in ..\Texas Instruments\Hercules\HALCoGen\v2.11\examples\TMS570LS31x\example_mibspiDma)

    Best Regards
    Prathap

  • 0 in reply to Prathap
    Expert 1180 points

    Thanks prathap. I will try the options that you suggested in next week and let you know the status.

    Thanks in advance.

  • 0 in reply to Prathap
    Expert 1180 points

    Thanks prathap. I will try the options that you suggested in next week and let you know the status.

    Thanks in advance.