LP-MSPM0G3507: HFCLK - External Osciallator as ADC clock source shows wrong sampling frequency in CCS theia

Kai Büchler

Part Number: LP-MSPM0G3507

Tool/software:

Hi,
I configured the available external oscialltor on the Launchpad to be the ADC clock source (HFCLK - 40Mhz). It is only sourcing the ADC, the source of the MCLK is SYSOSC. When changing the clock source of the ADC from ULPCLK to HFCLK, the calculated sampling rate goes down in CSS Theia. I assume is due to the additional 2-3 clock cycles for sync when not using ULPCLK.

I did a test measurement and noticed that the actual sampling rate is not as given by CSS Theia, but higher matching exactly the value given when ULPCLK is used.

I'm sure that in general the external oscialltor is used, since the time base is far more accurate compared to ULPCLK with SYSOSC.

Any ideas?

6 months ago

0 Cash Hao11 6 months ago

TI__Mastermind 46765 points

Hi,

It seems you have successfully use HFCLK as the ADC clock source. So, any issues?

Best regards,

Cash Hao

0 Kai Büchler 6 months ago in reply to Cash Hao11

Prodigy 35 points

Yes, there is an issue.

Kai Büchler said:
I did a test measurement and noticed that the actual sampling rate is not as given by CSS Theia, but higher matching exactly the value given when ULPCLK is used.

0 Cash Hao11 6 months ago in reply to Kai Büchler

TI__Mastermind 46765 points

Hi,

Okay, What sampling rates value you are getting from CCS Theia with HFCLK and ULPCLK?

Best regards,

Cash Hao

0 Kai Büchler 6 months ago in reply to Cash Hao11

Prodigy 35 points

I have 10bits sequential 4 Channels with 125ns sampling time and 2 conversions for HW averaging. With 40MHZ ULPCLK CCS Theia shows 416khz.100ns sampling time shows 454khz.

Changing to HFCLK (40MHz) and 100ns sampling time CCS Theia shows 400khz, but aligning the data with a parallel oscilloscope reading I can see it's 454khz.

That would mean the 2-3 cycles for clock sync are not needed, but the documentation states that's only the case for ULPCLK.

0 Cash Hao11 6 months ago in reply to Kai Büchler

TI__Mastermind 46765 points

Hi,

Could you show me which document shows it needs 2-3 cycles for clock sync?

Best regards,

Cash Hao

0 Kai Büchler 6 months ago in reply to Cash Hao11

Prodigy 35 points

Technical Reference Manual of the MSPM0G

0 Cash Hao11 6 months ago in reply to Kai Büchler

TI__Mastermind 46765 points

Hi,

Get it. I will run some test on it and check if this latency can also be bypassed through HFCLK.

Best regards,

Cash Hao

0 Kai Büchler 6 months ago in reply to Cash Hao11

Prodigy 35 points

Hi,
any updates? Thanks!

0 Cash Hao11 6 months ago in reply to Kai Büchler

TI__Mastermind 46765 points

Hi,

I get the same conclusion as yours, the ADC sample and conversion time makes no difference between sourcing from ULPCLK and HFCLK. So, it means that the sourcing from HFCLK can also bypass synchronization delay.

I will need to check with design team and see what we can do next.

Best regards,

Cash Hao

0 Kai Büchler 5 months ago in reply to Cash Hao11

Prodigy 35 points

Hi,
no update?

0 Cash Hao11 5 months ago in reply to Kai Büchler

TI__Mastermind 46765 points

Hi,

Sorry for the late response. I was on vocation last week. Design team will need some time to confirm it. And after confirmed, modifying the TRM will be an option.

Best regards,

Cash Hao

0 Kai Büchler 5 months ago in reply to Cash Hao11

Prodigy 35 points

Hello,
ok

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LP-MSPM0G3507: HFCLK - External Osciallator as ADC clock source shows wrong sampling frequency in CCS theia