Which interrupt registers and flags are used in MibSPI mode and compability spi mode

Hi Fumin Li

For both MIBSPI and Compatibility mode register INTVECT0 ( for Highlevel interrupt) and INTVECT1(For Low level Interrupt) hold the pending Interrupt status.

Read INTVECT0 / INTVECT1 register depending the on the Interrupt level enabled, and decode to figure out pending interrupt.

See below two scenarios:

1) To service MIBSPI Transfer group 0 (TG0) Transfer Complete  Low Level Interrupt do the following
       --- Read INTVECT1 ( For eaze assume you have it in variable "vec")
       --- Check for error ( If Vec is greater than 0x21 in case of MIBSPI mode is an error interrupt) , If yes then read the FLG reggister to find the error type and service accordingly.
       --- If no error ( i.e vec <= 21 )
            -> Check bit 0 to see whether it is suspended interrupt or not
            -> Bit (1-5) will contain the TG number and it can be serviced accrodingly

2) To service compatibility mode High Level Interrupt do the following
       --- Read INTVECT0 ( For eaze assume you have it in variable "vec")
       --- Ignore bit 0
       --- Read Bit ( 1-5)
                   --> Switch (Bit ( 1 - 5) )
                         -- case 11 --> Error interrupt check FLG register for more details
                         -- case 12 --> Receive Buffer Full interrupt - basically your receive interrupt, time to read the new received data..
                         -- case 13 --> Receive Buffer Overrun interrupt
                         -- case 14 --> Transmit Buffer Expty interrupt - basically your TX interrupt, time to put new data to transmit.

Hope this helps.. Please refer MIBSPI Interrupt vector 0 register description in TRM for more details,  Also try using HALCoGen tool, it will generate code for you with the ISR, all you have to do is to add Notification function which will be called in the ISR..

- Prathap

This is the code generated by HALCoGen ver2.09.000. And i add some comments and questions in the code section.

void spi1LowLevelInterrupt(void)
{
    unsigned vec = spiREG1->INTVECT1;

    if (vec > 0x100001U)   //Question1: It should be: if(vec > 0x21), right?
    {   // Question2: this is in compability mode, right?
        unsigned flags = spiREG1->FLG & (spiREG1->LVL & 0x035F);
        spiREG1->FLG = flags;
        spiNotification(spiREG1, flags);
    }
    else  //Question3: this is in mibspi mode, and it not handle the different kinds of transmission errors and receive overrun interrupts, which registers are these error flags from?  Are the flag different between SPI receive buffer RAM and  SPIFLG(offset=0x10) ? which registers should manually clear ?
    {
        spiGroupNotification(spiREG1, ((vec & 0x3FU) >> 1U) - 1U);
    }
}

Hi Li,

Yes you are right, it's a bug in 2.09.000

You should be using the latest HALCoGen, I think it is 2.11. .Download link --> http://www.ti.com/tool/halcogen
Note: The spi driver does not support the compatibility mode for mibspi yet.
But just for reference how to handle compatibility mode, try generating code for TMS570LS31x family -->TMS570LS3137ZWT for SPI2 adn SPI4 module. (Spi.c and spi.h)
TMS570LS31x family has 3 mibspi and 2 dedicated SPI(non buffered, similar to mibspi compatibility mode).

Please press Verify Answer if your question is answered.. Thanks!

Best Regards
Prathap

Dear Prathap,

Thanks for your great support and great help.

I download HALCoGen from your giving website, it is not 2.11, but ver2.10. And i setup this version and do as you tell me, but i think it is still not answer my questions.

The questions are raised in the previous post, please refer to the post..

Hope Ti can give more detailed answers about interrupt handling and error interrupt tests.

Hi Prathap,

Thanks for your great answer, i understand now.

 additional question, Are the flags different between SPI receive buffer RAM and  SPIFLG(offset=0x10) ? Is there any flag registers that should be manually cleared ?

And so,in the TRM "SPNU489C", this sentece is wrong:

Hi Li,

No, that sentence is correct.. In conpatibility mode you will not access any of MIBSPI RAM.
By default / After reset the MIBSPI module is in compatibility mode. You will not have access to MIBSPI RAM Unless MSPIENA bit in MIBSPIE register is set. which you should not set for compatibility mode.

Configuration Registers
1) SPIGCR0
2) SPIINT0
3) SPILVL
4) SPIPC0 - SPIPC8
5) SPIDAT1
6) SPIDELAY
7) SPIDEF
8) SPIFMT
9) SPIGCR1

Status Registers
9) SPIINTVECT0 / 1
10) SPIFLG

Only FLG register has to be cleared manually ( Some of the status bits are cleared by reading/writing other registers, for Eg: In TX or RX ISR reading INTVECTx register will clear TXINT or RXINT flag ), I would advice to follow the register description section for exact FLG clearing procedure.

Best Regards
Prathap

Hi prathap,

In mibSPI mode, are the flags different between SPI receive buffer RAM and  SPIFLG(offset=0x10) ?