AM263P4: EPWMs out of sync by 1 clock cycle

I think this is a recognised (but not well documented) phenomenon.

I found the following in C:\ti\mcu_plus_sdk_am263px_10_01_00_34\examples\drivers\epwm\epwm_synchronization\epwm_synchronization.c

    /* 
    When the Sync Pulse arrives, the rising edge is detected and the EPWM holds the state of the Sync singal present. 
    The phase shift value is loaded to the TB Counter of EPWM on the next valid TBCLK. 
    This may cause a TBCLK delay on the "Synced" PWM with the "Syncing" PWM. Hence the 1 count difference in the validation 
    */

I could not find a similar note in the TRM but that is not to say it isn't there. Like I say, not well documented.

Hello Huey, Kier,

I will need to review this with our software expert for EPWM who will be back on Monday. If the TRM is lacking information on this I can work to get it added for future revisions.

Best Regards,

Ralph Jacobi

Hello Huey,

I was able to confer with another EPWM expert who is familiar with the behavior you are seeing.

As Kier was mentioning, this is a known issue, and you should use a TBPHS value of 1 or 2 depending on the SYSCLK speed. Based on the delay here, probably a TBPHS value of 1 would work for this.

Alternatively, another solution is not using the SYNC feature at all. The PWMs should start simultaneously after TBCLKSYNC is enabled.

Best Regards,

Ralph Jacobi

Thanks for the response.  From what I can see, when using up counter, the delay is 1 Ttbclk.  But when using up/down count, the sync is offset by 2 Ttbclks. T Fpwm is 40kHz.  Can you confirm that using up/down counter will result in 2x the offset?  

I was curious if we could use compare D to generate the sync out signal.  EPWMSYNCOUTEN[CMPDEN]=1.   

The question I have is, when using up/down counter, which compare will trigger the sync pulse?  On up count, down count, or both?

Thanks.

Hi Huey,

The delay from internal module to target module is either:

• if (TBCLK = EPWMCLK): 2 x EPWMCLK
• if (TBCLK < EPWMCLK): 1x TBCLK

Up/down counter shouldn't double the offset.

There's a bit for SYNCDIR that determines if the count is up or down after a event. This could influence the behavior. Can you check both bit settings and see if there is a difference in the offset based on that?

Best Regards,

Ralph Jacobi

Hi Ralph,

I took the epwm_synchronization example and did the following examples in sequential order.

TBCLK = 200MHz / (8*1) = 25MHz   ->  Ttbclk = 40ns.   Compared EPWM0 -> EPWM1 synchronization.

1. Set EPWM1 to no phase shift.

• Changes: EPWM1 Phase Shift Value(TBPHS)=0.  epwm_synchronization.c::Line146 change ClockP_sleep(5) -> (500)
• Result: EPWM1 lags EPWM0 by 40ns=1xTBCLK
• As mentioned up counter with TBCLK < EPWMCLK has 1xTBCLK lag

2. Changing to up/down counter mode.

• Both EPWM0,1 changed to up/down counter mode. 
• Sysconfig warns EPWM1 in up/down counter mode: Count down dir with phase of 0 not allowed
• Changed Counter Mode After Sync -> count up
• Result: EPWM1 lag 40ns=1xTBCLK

3. Changing TBCLK to 200MHz.

• Result: EPWM1 lags 10ns=2xTBCLK

This confirms your comments above.  That the 2xlag is due to the TBCLK=EPWMCLK.  It does not depend on SYNCDIR or clock mode.

Thanks for clarifying how the sync works.

2 Questions:

• Is this an expected chip functionality? I did not see this behavior mentioned in TRM nor the Errata.
• When using CMPD to generate SYNCOUT for EPWM0 using up/down counter, is the sync pulse generated on the up count or down count?  And is this configurable? 

Thanks

PS.  I have decided to not use the sync feature at all and simply ensure all TBCTRs are zero'd when TBCLKs are enabled during initialization.   Just would be nice to understand how sync works in case we need to sync during operation mode.