AM2432: GPIO power on abnormality

Hello zhanglongc,

Thank you.

zhanglongc said:

Recently, we found during testing that the GPIO Y7 of AM2432 defaults to external pull-up, with the system initialization

Did you mean cold reset or any other initialization.

I will need a PDF schematic of the GPIO connection to do a quick check.

Regards,

Sreenivasa

Hi Sreenivasa,

Customer sch as attach. Thanks for support.

6318.pdf

BR,

Biao 

Hello Biao,

Thank you.

Let me review and comeback.

Can you confirm if customer is seeing this issue during reset or after the software starts to run?

is the PRU being configured ?

regards,

Sreenivasa

Hello Biao,

To be able to confirm the behavior is during reset, can you please have the waveform captured along with the RESETSTATz reset status output.

Regards,

Sreenivasa

Hi Sreenivasa,

Thanks for support, I will let customer capture it.

BR,

Biao

Hi Sreenivassa:

    Thank you for you reply,i'm sorry to reply delay,Based on your suggestion, I added tests for 3.3V, MCU_PORZ, GPIO_Y7, and RESENTSTATz power-up waveforms.The figure belowAs shown in the figure below。

I suggest you test in the lab or EVM to see if you have the same problem!

Hello zhanglongc,

Thank you.

Help me understand the 3.3V net, is the the IO supply - not sure why this is rising along with MCU_PORz?

I am not sure if this is due to time base. Can you please expand and capture the plot.

Does customer have a pullup on the GPIO_Y7 or pulldown. The schematic shows pulldown.

Regards,

Sreenivasa

Hi Sreenivassa:

     Thank you.

     1、The GPIO_Y7 is pullup not pulldown,we just make a reservation in the schematic design, the attribute labeled “NO”, that the PCBA does not solder it!

    2、 IO supply（3.3V） is not  rising along with MCU_PORz, please see xpand and capture the plot,shown in the figure below.

    because GPIO_Y7 pullup,so GPIO_Y7  rising along with  IO supply（3.3V）,MCU_PORZ is pullup when all power supply ok,RESENTATz rising along with MCU_PORz.In summary, my shall hardware design and power-up timing is OK. Please help me to confirm what is the cause of this problem as soon as possible, thanks!

Hello zhanglongc,

Thank you.

Sorry but i do not understand the issue.

The IO is pulled to 3.3V supply and you see a 3.3V.

If you are concerned the internal pull is enabled after reset - the IO is expected to go high along with the reset and to test that you may have to DNI the external pullup.

The IO has a leakage of 10 uA max specified. Can you DNI the pullup and make the same measurement to confirm the internal pull is being enabled.

Regards,

Sreenivasa

Hi Long,

There is some mismatch in the SCH you sent to us, in the PDF, pls check why 2CPUID0 is pull down.

BR,

Biao

Hi Sreenivassa:

    Thank you.our board has two pcs AM2432 ,we use the external pull-up and pull-down as the ID for the 2-chip AM2432, so the software for this pin is configured for input mode, so I don't think it makes sense to measure it after you tell me to DNI it.also pillup 10k ,the leakege current meets specifications.

1CPU_ID:1010   2CPU_ID:0101

Hello zhanglongc,

Thank you.

Please refer to the waveform you shared that show the IO being 3.3V along with the supply.

Is this measured when the external pull is high or low?

I assume this is measured when the pullup is mounted.

Can you please share the waveform with external pulldown.

Please be aware i still do not understand the issue to analyze or support.

Regards,

Sreenivasa

Hello zhanglong, Biao

Thank you and appreciate resolving the issues.

Was the PADCONFIG the issue or was there some other issue?

Regards,

Sreenivasa

Hi Sreenivasa,

Yes, I guess it is padconifg issue, customer don't setting the pull, the padconfig enable the pull down default, it become normal after customer setting it to pull disable. in additional, can you share what is the internal pull down resistor value? 

BR,

Biao 

Hello Biao,

Thank you.

7.7.6 LVCMOS Electrical Characteristics

15..30 K 

Y7 V4 PRG1_PRU0_GPO0
PADCONFIG46
0x000F40B8
PRG1_PRU0_GPO0 0 IO 0 7 Off / Off / Off Off / Off / Off 1.8 V/3.3 V VDDSHV2 Yes PU/PD LVCMOS
PRG1_PRU0_GPI0 1 I 0

The IO buffers are pulls are off during and after reset.

I suspect there is some configuration that enables the pull.

Regards,

Sreenivasa

Hi Sreenivasa,

   Thank you.

   I know the IO buffers are pulls are off during and after reset.but  it appears that the level is pulled down is RESET has been released, yesterday I checked the software configuration, GPIO_Y7 is only configured as input mode, no pull is configured, after we pin pull disable the GPIO level is OK, so I want to know is the GPIO pull down by default after RESET is released?

Figure 1 GPIO_Y7 Before Configuration Modification

Figure 1  GPIO_Y7 configuration modified

Hello zhanglong, Biao

Thank you.

zhanglongc said:

GPIO_Y7 is only configured as input mode, no pull is configured, after we pin pull disable the GPIO level is OK, so I want to know is the GPIO pull down by default after RESET is released?

For any further analysis, i will need your support to DNI any external pulls on the Y7 pin (for both the SOCs) and capture the pin status along with MCU_PORz input, RESETSTATz output during power-up.

Regards,

Sreenivasa