• State Resolved
  • Locked Locked
  • Replies 9 replies
  • Subscribers 32 subscribers
  • Views 421 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

AM2634: Ethernet

TEMC
Intellectual 955 points
Part Number: AM2634

Tool/software:

Hi all,

In our custom design with AM2634 we implemented an ethernet circuit using phyther KSZ8041FTLI-TR, while we are testing this circuit, we observed some issues in data transmission and reception, we are losing some packets while transmitting and receiving packets, so we tested using far end loop back and near end loop back, if far end loop back i.e switch to phyther loop back no packets were missing but while testing between controller to phyther we observed data miss some packets are getting missed. please help us to resolve the issue 

  • 0
    TI__Expert 5376 points

    Hello,

    Please expect a response by Monday, as it is an optional holiday in TI India.

    Thanks,

    Sahana

  • 0 in reply to Sahana H G
    Intellectual 955 points

    Hello,

    Any update regarding the issue

  • 0
    Intellectual 955 points

    We used RMII as interface for MAC to Phy, Is there any issue with utilization of RMII interface in AM2634

  • 0 in reply to TEMC
    TI__Expert 4940 points

    Hello,

    Apologies for the delay, do you have clearer photos of your connections so that I can double check the MAC to PHY connections?

    For missing packets, a likely cause is the timing. We have a enet_cpsw_loopback example as part of our SDK, are you able to test with that example? It would have to be modified for RMII.

    Regards,
    Susan

  • 0 in reply to Susan Moore
    Intellectual 955 points

    Could you please share your mail I will send you the schematic

  • 0 in reply to Susan Moore
    Intellectual 955 points

    Yes, we have tested the MAC loopback using the enet_cpsw_loopback example by configuring the interface as RGMII as in TRM it was mentioned that the MAC Loopback functionality is applicable for RGMII only. Here attaching the reference of AM263x Register Addendum.

  • 0 in reply to TEMC
    Intellectual 955 points

    Hi,

    Any update regarding the issue

  • 0 in reply to TEMC
    TI__Expert 4940 points

    Hello,

    Apologies for the delay, I did not receive notification of your previous messages.
    I looked at the schematic, and I did not see anything I am concerned about right away. I spoke with our software expert, and we believe you may need to add some delay to the RMII lines for internal MAC loopback depending on why the packets are being dropped.
    Unfortunately we don't have any examples that add a delay. 
    Are you able to print the statistics to see why the packets were dropped? Knowing if they were dropped because of an error or because there are overrun packets will help determine the best way to resolve the issue. In addition, I would check that the receive flow control is enabled.
    I am not aware of any issues regarding the utilization of RMII, but I have reached out the software team to see if they have any information.
    Regards,
    Susan

  • 0 in reply to Susan Moore
    Intellectual 955 points

    Hi Susan,

    As we using external crystal oscillator for PHY and MAC reference clock, the clock output functionality of CPSW for RMII should be disabled but we have not disabled it earlier. Now we have tested by disabling the clock output functionality of CPSW for RMII in CPSW control register this resolved the issue we tested upto 1500 octets we received without any miss/corruption of data. Thank you for support.

    Regards,

    TEMC