Tool/software:
Hello team,
Few questions:
- I noticed that in all the examples OCRAM is defined as a 2 MB with a start address of 0x70000000 and there is no option to change that to 3 MB, should I add another 1 MB region starting with the address of L2OCRAM_BANK4?
- Is there any constraint on assigned memory sizes to each core? for example, can I have the following hypothetical assignment:
- Core 1_0: Start: 7018 0000, Size: 0x20000
- Core 1_1: Start: 701A 0000, Size: 0x60000
- Can I have parts of the OCRAM or that extra 1 MB that I will define shared between cores and protected by a spinlock? I would need one core to be sampling and filling a buffer, and another core reading and processing the sampled data.
- Can I reduce the size of the SBL region if I'm using the provided CAN SBL with a minor modification, assuming it would still fit in the assigned region?