This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

AM263P4-Q1: OCRAM MPU region assignment in sysconfig

Part Number: AM263P4-Q1


Tool/software:

Hello team, 

Few questions:

  1. I noticed that in all the examples OCRAM is defined as a 2 MB with a start address of 0x70000000 and there is no option to change that to 3 MB, should I add another 1 MB region starting with the address of L2OCRAM_BANK4? 
  2. Is there any constraint on assigned memory sizes to each core? for example, can I have the following hypothetical assignment:
    1. Core 1_0:  Start: 7018 0000, Size: 0x20000
    2. Core 1_1:  Start: 701A 0000, Size: 0x60000
  3. Can I have parts of the OCRAM or that extra 1 MB that I will define shared between cores and protected by a spinlock? I would need one core to be sampling and filling a buffer, and another core reading and processing the sampled data.
  4. Can I reduce the size of the SBL region if I'm using the provided CAN SBL with a minor modification, assuming it would still fit in the assigned region? 

  • Hi Ahmed,

    Apologies for delay in response.

    noticed that in all the examples OCRAM is defined as a 2 MB with a start address of 0x70000000 and there is no option to change that to 3 MB, should I add another 1 MB region starting with the address of L2OCRAM_BANK4? 

    Yes, this can be done for adding rest of the RAM memory for MPU Configurations.

    Is there any constraint on assigned memory sizes to each core? for example, can I have the following hypothetical assignment:
    1. Core 1_0:  Start: 7018 0000, Size: 0x20000
    2. Core 1_1:  Start: 701A 0000, Size: 0x60000

    There is no limitation on size of memory that can be defined for each core. Just make sure that it is not conflicting. You can use memory configurator tool in syscfg for this.

  • Can I have parts of the OCRAM or that extra 1 MB that I will define shared between cores and protected by a spinlock? I would need one core to be sampling and filling a buffer, and another core reading and processing the sampled data.

    Yes that is possible, please look at IPC notify example for reference:

    software-dl.ti.com/.../EXAMPLES_DRIVERS_IPC_NOTIFY_ECHO.html

    1. Can I reduce the size of the SBL region if I'm using the provided CAN SBL with a minor modification, assuming it would still fit in the assigned region? 

    If it fits you can make the chnage, but you need to make sure the code does not overflow.