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AM2432: Multi-Core Simulation on CCS

Kevin Peng
Expert 4188 points
Part Number: AM2432
Other Parts Discussed in Thread: TDA4VH

Tool/software:

Hi TI Experts,

Customer is working on AM2432 SDK9.2.

Customer is okay to only connect 1 core like R50-0 to debug on CCS with no problem shown below.

However, if customer wants to debug an additional core like R51-0 on CCS (when R50-0 is already connected), they will have the below problem.

The details of this problem is showing below.

May I know could you provide some guide to help customer run multi-core debug on CCS please?

Thanks,

Kevin

  • 0
    TI__Expert 7395 points

    Hi Kevin,

    What SBL is flashed on your board?

    If you just power cycle the board and connect to R5F1_0 core, do you still see the same error?

    Regards,

    Nitika

  • 0 in reply to Nitika Verma
    TI__Expert 4188 points

    Hi Nitika,

    Thanks for your reply!

    Customer is using no boot mode, without having SBL. In no boot mode, they have to connect R5F0_0 core firstly, they could not just power cycle the board and connect to R5F1_0 core.

    The background is customer has mass production experience on TDA4VH before, and they could do multi-core simulation on CCS in TDA4VH before. However, it seems that in AM24 they have some problems with it.

    Thanks,

    Kevin

  • 0 in reply to Kevin Peng
    TI__Guru 54168 points

    Hi Kevin,

    Which version of MCU+SDK are you using?

    What is the example you are trying to load? Before loading the *.out binary on the core are you doing a CPU reset?

    Regards,

    Tushar

  • 0 in reply to Tushar Thakur
    TI__Expert 4188 points

    Hi Tushar,

    Thanks for the reply.

    As mentioned customer is working on SDK9.2, no boot mode when testing CCS.

    They are using the IPC Notify example.

    They did power off & power on the board before loading the *.out binary.

    After power off & power on the board, they firstly load to R5F0_0, there is no problem, and without doing any CPU reset at this moment, they load the binary to R5F1_0, but after doing that it will occur the problem mentioned earlier.

    Thanks,

    Kevin

  • 0 in reply to Tushar Thakur
    TI__Expert 4188 points

    Hi Tushar,

    An update that customer tested the original IPC notify example with no boot mode, and they could load R5f1_0 with no issues. It seems like they have some modifications in the configurations in their project setting. And customer is looking at the difference which may cause this problem.

    Thanks,

    Kevin

  • 0 in reply to Kevin Peng
    TI__Guru 54168 points

    Hi Kevin,

    Let me check the above at my end and revert back. Please allow some time.

    Regards,

    Tushar

  • 0 in reply to Kevin Peng
    TI__Guru 54168 points

    Hi Kevin,

    Kevin Peng said:
    It seems like they have some modifications in the configurations in their project setting. And customer is looking at the difference which may cause this problem.

    Can you please provide the modification that is done after which the binary is not loaded to R5F1-0 core?

    Regards,

    Tushar

  • 0 in reply to Tushar Thakur
    TI__Expert 4188 points

    Hi Tushar,

    There is quite a lot difference in customer configurations compared to the default example.

    We found a workaround to use SBL boot, instead of no boot mode, then customer could successfully load the R5F1_0 core now.

    Thanks,

    Kevin