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AM263P4-Q1: Lauterbach TRACE32 Instances Missing?

Part Number: AM263P4-Q1

Tool/software:

Hello,

I ran '_am263px_allcoretype_connect.cmm' script expecting to see at four instances of TRACE32 for ARM-R5xxx. However, I only get the following:

 

My project is R50_0, R51_0 and R51_1. (R50_1 is in lockstep mode).

I want to use Data,LOAD.Elf for R50_0, R51_0 and R51_1.

<Question>

  • It seems that 'ARM-R5SS0' = R50_0 and 'ARM-R5SS1' = R51_0, is that correct?
  • If so, where is the instance for R51_1 in order to load its .out file please?
  • If not, please correct my misunderstanding.

Thank you.

  • Hello,

    The am263px_allcoretype_connect.cmm is a test script to show that all core types can be attached to.  That script for R5's calls the _am263px_r5ss.cmm attach helper.  The call parameters for that script are AMP1, AMP2 or SMP.   The SMP allows for debugging 2 cores of a cluster concurrently (it sets a break point at the same spot in both, this is used if the binary is the same between the cores).  If the cores in a cluster are independent then a GUI for each is needed.

    For you you describe you would create 3 instances:
      IC R5SS0_0 DO "&path/_am263px_r5ss.cmm" R5SS0 AMP1         ; core 1 of 2 in split
      IC R5SS0_1 DO "&path/_am263px_r5ss.cmm" R5SS0 AMP2         ; core 2 of 2 in split
      IC R5SS1_x DO "&path/_am263px_r5ss.cmm" R5SS1 AMP1         ;  core 1 of 1 in lock
    You would have R5SS1 in lock before attaching to it.
    The bare metal scripts in x_gel_to_cmm are mostly meant for unit test without initial firmware.  For development with the TI SDK you may need to add clean attach points (some while(1) spin) early into applications to do a ~late attach, then debug (this would likely mean only a symbol load as the code would come from flash).
    Regards,
    Richard W.
  • Thank you Richard but I'm still struggling.

    I'm not certain but since SS0 is intended to be lockstep (not SS1) then my simple script should look like this, no?

      IC R5SS0 DO "&path/_am263px_r5ss.cmm" R5SS0 AMP1 ;core 1 of 1 in lock
      IC R5SS1 DO "&path/_am263px_r5ss.cmm" R5SS1 AMP1 ;core 1 of 2 in split
      IC R5SS1 DO "&path/_am263px_r5ss.cmm" R5SS1 AMP2 ;core 2 of 2 in split

    But when I run this, I get the following:

    Apologies, a bit of a noob with Lauterbach.

  • Hello,

    Yes, what you show for a connection is is the right flow.   You would need to ensure the control for the lock step was in place before trying to connect.

    The intercom is failing as its necessary to start an instance before calling it.  IC = Intercom, and it takes a "name-handle" parameter R5SS0 in the example.  That "name-handle" is an alias for a networking port address.  That must be first created (like is in the allcore connect script).  Once its created it can be called with parameters.

    Regards,
    Richard W.
  • Hi Richard,

    OK, I got as far as creating two instances and releasing both cores in SS1. I'm using the following script now:

    This seems to make all the right noises:

    However, this still only gives me two instances, one for each subsystem. As far as I can see, I can only view one set of Registers in SS1, I assume this is Core 0 (aka. R5FSS1_0).

    The questions remain though:

    - How would I view the registers of the second core in SS1 (R5FSS1_1)?

    - How would I load the ELF file to the second core in SS1 (R5FSS1_1)?

    Thank you.

  • Hello,

    What to do depends on the code being run.   Some configurations of autosar use the same code across cores, in those cases you would send an "SMP" argument (things like break points are set to both cores in this config).  If each core uses its own code then you would start 3 GUI instances.   Just reuse the pattern above and have a "R5SSx AMP1 + R5SSy AMP1 + R5SSy AMP2".  You can then load a given core directly using the GUI instance or its handle gotten via a script. 

    It may be worth looking into some TRACE32 specific training given by Lauterbach.  They will be able to accelerate your ramp in tool usage.  They do have these boards in their farms and will give the best tool specific help.

    Regards,
    Richard W.
  • Yes, I need 3 GUI instances because I have unique code in each core.

    have a "R5SSx AMP1 + R5SSy AMP1 + R5SSy AMP2"

    Agreed but what is the syntax for R5SSy AMP2 please? That is the nub of the issue.

    Following the pattern, I have:

    Above I'm trying to creating a second instance of R5SS1 (R5SSy) on lines 34 to 39 and passing the AMP2 argument. However, only one instance (for subsystem 1), the last instance to be created in the script, remains:

    The first subsystem 1 instance is missing, presumably closed when the second instance was created.

    Are you able to try this your end please?

  • Actually, I may have just stumbled on the correct syntax:.

    Looks like the argument to INTERCOM.PING() and _am263px_r5ss.cmm should remain as 'R5SS1' (green) but all other subsytem references are R5FSS1_1 (yellow):

    I repeated the same pattern for the first instance.

    I now have 3 GUIs to work with.

    Remains to be seen if these are actually connected to the right core. Here's the script I now have:

    ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
    ; Launch/connect all cores for AM263px
    ; 28 Aug 23 - Richard Woodruff - Adapt AM263 to AM263px
    ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
    ; Bare metal all core test to run on:
    ;   GP:     All core connect
    ;   HS-FS:  SW1: FLED(0,1,0,1) : All core connect
    ;   HS-xx:  SW1: !FLED : Use null SBL to unlock (else no HSM and watchdog)
     &path=OS.PPD()
    
    ;;;;;;;;;;;;;;;;;;;;;; SOC Setup ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
    ;; Initial scripts use AHB-AP to bring up cores
     TITLE "TRACE32 for ARM-CR5-EAHB - MASTER"
     DO "~~~~/AM263Px.cmm"    ; enable all power & clocks & load menus
     wait 1s
    
    ;;;;;;;;;;;;;;;;;;;;;;; R5FSS;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
    ;; CR5: (R5SS0,R5SS1) x (SMP,AMP1,AMP2)
    ;;;;;;;;;;;;;;;;;;;;;;; R5F_SS0 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
     IF !INTERCOM.PING(R5SS0)
      TargetSystem.NewInstance R5SS0 /ARCHitecture ARM
     IC R5SS0 TITLE "TRACE32 for ARM-R5SS0_0"
     DO "&path_AM263Px_common_cmm" R5F_SS0_CoreA_unhalt
     IC R5SS0 DO "&path/_am263px_r5ss.cmm" R5SS0 AMP1
     IC.WAIT R5SS0
    ;;;;;;;;;;;;;;;;;;;;;;; R5F_SS1 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
     IF !INTERCOM.PING(R5SS1)
      TargetSystem.NewInstance R5SS1_0 /ARCHitecture ARM
     IC R5SS1_0 TITLE "TRACE32 for ARM-R5SS1_0"
     DO "&path_AM263Px_common_cmm" R5F_SS1_CoreA_unhalt
     IC R5SS1_0 DO "&path/_am263px_r5ss.cmm" R5SS1 AMP1
     IC.WAIT R5SS1_0
     
     IF !INTERCOM.PING(R5SS1)
      TargetSystem.NewInstance R5SS1_1 /ARCHitecture ARM
     IC R5SS1_1 TITLE "TRACE32 for ARM-R5SS1_1"
     DO "&path_AM263Px_common_cmm" R5F_SS1_CoreB_unhalt
     IC R5SS1_1 DO "&path/_am263px_r5ss.cmm" R5SS1 AMP2
     IC.WAIT R5SS1_1
    
    ENDDO

  • OK, the 3 GUIs should allow controlling each core independently.  You can load some unique code onto each, or do 'data.assemble' (create simple per core unique code code) then set the pc to step it.

  • Thanks for the leg up Richard.

    I have confirmed the correct cores are attached via the MPIDR register.

    I have also modified _am263px_r5ss.cmm and loaded the correct program for each code and they each run to main(). So I'm good to go....almost.

    Last question please: I wish to start (Go) all 3 instances simultaneously. How to 'Go' for all cores simultaneously please?

    The equivalent in CCS would be clicking on core Group 1 and hitting Resume:

  • Hello,

    Thanks for sharing the feedback about your progress.  The MPIDR is a good way to get confidence in the core to GUI mapping.  My method was based on address mappings and what is in specifications which was correct, but the MPIDR is even a better correlation point.

     For grouping with action rules the common method would be to use the synch command. By default it will use a debugger network port based synchronization.  If a faster method is needed CTI's can be setup.  I made a short video to demonstrate on a am263p EVM.

    Regards,
    Richard W.
  • Many thanks for the video Richard, just what I needed!

    For subsequent readers, you can just put two slaves separated by a space in the master's connect list: