MSPM0G3507: TRM error in SYSPLL setup example [SLAU846B Sec 2.3.1.3.1]

Hi, Bruce

Bruce McKenney said:

Steps (9)-(10) start the PLL, then Step (11) connects the PLL output to the HSCLK using MCLK2XVCO. But once the PLL is enabled, MCLK2XVCO can't be set [observed behavior], so the HSCLK (and thus MCLK) ends up with no clock source.

Do you have this test code?

I intend to try from my side.

Regards,

Helic

I don't have the code here; I'll plan to post it this evening. It's really just a step-by-step implementation of the Example. [I've observed that every PLL has something unusual somewhere, so I started simple.]

It's fairly typical of a PLL (sub)system that some/all of the configuration is locked once the PLL starts ticking, but the TRM doesn't really mention that about SYSPLL, nor (more to the point) which particular fields are locked.

One clue (I just noticed) is the definition of CLKSTATUS:SYSPLLBLKUPD [Ref Table 2-53], which is described as applying to all of SYSPLLCFG0/1 (and SYSPLLPARAM0/1), which would include MCLK2XVCO. [I suppose it would be "blocked" if the SYSPLL is running, but it doesn't say that either.]

As I mentioned: I already (now) know the answer; I was just concerned about the next person who tries this.

That's great!

Of course, if you don't have such a demo, I will try to setup one.

It's better to have one, this will save more time!

Thanks for your feedback~

Um, are you looking for something different from what I posted (above)?

Hi Bruce,

I tried your suggestion, "Setting PLLFAIL to 1 will use the TRM order," in the DL_SYSCTL_configSYSPLL() function. With this change, I am getting a better result for my MSPM0G1507 frequency out-of-tolerance issue.

Please check the following link for more details: MSPM0G1507 - Frequency Out of Tolerance Issue

Could you confirm if this modification is necessary when using SYSPLL, or is there an alternative approach to ensure better accuracy?

I'm not quite sure what change you made (and to what), but I think it's interesting that it had an effect on your results. [I haven't commented there since Helic seems to be far ahead of me.]

One difference I noticed is that in your case Sysconfig decided on QDIV=(10-1) and RDIV2X=(4-1) while I was using QDIV=(5-1) and RDIV2X=(2-1).

Each of these takes SYSOSC=32MHz and puts out MCLK=80MHz, but yours runs the clocks twice as fast {VCO=160MHz,CLK2X=320MHz} vs {VCO=80MHz, CLK2X=160MHz}. This isn't out of spec, but maybe there's a phenomenon in there somewhere?

Hi Bruce,

Thank you for clarification, 

 I suspect something might be missing or incorrectly sequenced in the "DL_SYSCTL_configSYSPLL()" function implementation, which could be affecting the SYSPLL initialization process.

With respect to the topic here, configSYSPLL is using the correct order (different from that in the TRM). 

What change did you make that seemed to improve your results?

He reset the device after device completely powering up, he get a better clock accuracy.

We reinitialize the clock function, yeah after soft reset also I am getting better accuracy 

 // for any clock change the SYSOSC must be at 32MHz and PLL should be disabled
    DL_SYSCTL_setSYSOSCFreq(DL_SYSCTL_SYSOSC_FREQ_BASE);
    DL_SYSCTL_enableSYSOSCFCLExternalResistor();
    DL_SYSCTL_disableHFXT();
    DL_SYSCTL_disableSYSPLL();

    
 
        static const DL_SYSCTL_SYSPLLConfig SYSPLLConfig_80Mhz = 
        {
            .inputFreq              = DL_SYSCTL_SYSPLL_INPUT_FREQ_16_32_MHZ,
            .rDivClk2x              = 3,
            .rDivClk1               = 0, 
            .rDivClk0               = 0,
            .enableCLK2x            = DL_SYSCTL_SYSPLL_CLK2X_ENABLE,
            .enableCLK1             = DL_SYSCTL_SYSPLL_CLK1_DISABLE, 
            .enableCLK0             = DL_SYSCTL_SYSPLL_CLK0_DISABLE,
            .sysPLLMCLK             = DL_SYSCTL_SYSPLL_MCLK_CLK2X,
            .sysPLLRef              = DL_SYSCTL_SYSPLL_REF_SYSOSC,
            .qDiv                   = 9,
            .pDiv                   = DL_SYSCTL_SYSPLL_PDIV_2
        };
        /*PLL setup and Clock dividers*/
        DL_SYSCTL_configSYSPLL((DL_SYSCTL_SYSPLLConfig *) &SYSPLLConfig_80Mhz);
        DL_SYSCTL_setMCLKSource(SYSOSC, HSCLK, DL_SYSCTL_HSCLK_SOURCE_SYSPLL); 
        DL_SYSCTL_setULPCLKDivider(DL_SYSCTL_ULPCLK_DIV_2);
        DL_SYSCTL_configSYSPLL((DL_SYSCTL_SYSPLLConfig *) &SYSPLLConfig_80Mhz);

I have attached Code snippet for your reference.

Please check the following two scenarios:

1️⃣ With Default Clock Initialization Code
Result: Clock is not accurate (Set: 2kHz, get: 2025-2030Hz tested with 5 sample boards).

void DL_SYSCTL_configSYSPLL(DL_SYSCTL_SYSPLLConfig *config)
{
    /* PLL configurations are retained in lower reset levels. Set default
     * behavior of disabling the PLL to keep a consistent behavior regardless
     * of reset level. */
    DL_SYSCTL_disableSYSPLL();

    /* Check that SYSPLL is disabled before configuration */
    while ((DL_SYSCTL_getClockStatus() & (DL_SYSCTL_CLK_STATUS_SYSPLL_OFF)) !=
           (DL_SYSCTL_CLK_STATUS_SYSPLL_OFF)) {
        ;
    }

    // set SYSPLL reference clock
    DL_Common_updateReg(&SYSCTL->SOCLOCK.SYSPLLCFG0,
        ((uint32_t) config->sysPLLRef), SYSCTL_SYSPLLCFG0_SYSPLLREF_MASK);

    // set predivider PDIV (divides reference clock)
    DL_Common_updateReg(&SYSCTL->SOCLOCK.SYSPLLCFG1, ((uint32_t) config->pDiv),
        SYSCTL_SYSPLLCFG1_PDIV_MASK);

    // save CPUSS CTL state and disable the cache
    uint32_t ctlTemp = DL_CORE_getInstructionConfig();
    DL_CORE_configInstruction(DL_CORE_PREFETCH_ENABLED, DL_CORE_CACHE_DISABLED,
        DL_CORE_LITERAL_CACHE_ENABLED);

    // populate SYSPLLPARAM0/1 tuning registers from flash, based on input freq
    SYSCTL->SOCLOCK.SYSPLLPARAM0 =
        *(volatile uint32_t *) ((uint32_t) config->inputFreq);
    SYSCTL->SOCLOCK.SYSPLLPARAM1 =
        *(volatile uint32_t *) ((uint32_t) config->inputFreq + (uint32_t) 0x4);

    // restore CPUSS CTL state
    CPUSS->CTL = ctlTemp;

    // set feedback divider QDIV (multiplies to give output frequency)
    DL_Common_updateReg(&SYSCTL->SOCLOCK.SYSPLLCFG1,
        ((config->qDiv << SYSCTL_SYSPLLCFG1_QDIV_OFS) &
            SYSCTL_SYSPLLCFG1_QDIV_MASK),
        SYSCTL_SYSPLLCFG1_QDIV_MASK);

    // write clock output dividers, enable outputs, and MCLK source to SYSPLLCFG0
    DL_Common_updateReg(&SYSCTL->SOCLOCK.SYSPLLCFG0,
        (((config->rDivClk2x << SYSCTL_SYSPLLCFG0_RDIVCLK2X_OFS) &
             SYSCTL_SYSPLLCFG0_RDIVCLK2X_MASK) |
            ((config->rDivClk1 << SYSCTL_SYSPLLCFG0_RDIVCLK1_OFS) &
                SYSCTL_SYSPLLCFG0_RDIVCLK1_MASK) |
            ((config->rDivClk0 << SYSCTL_SYSPLLCFG0_RDIVCLK0_OFS) &
                SYSCTL_SYSPLLCFG0_RDIVCLK0_MASK) |
            config->enableCLK2x | config->enableCLK1 | config->enableCLK0 |
            (uint32_t) config->sysPLLMCLK),
        (SYSCTL_SYSPLLCFG0_RDIVCLK2X_MASK | SYSCTL_SYSPLLCFG0_RDIVCLK1_MASK |
            SYSCTL_SYSPLLCFG0_RDIVCLK0_MASK |
            SYSCTL_SYSPLLCFG0_ENABLECLK2X_MASK |
            SYSCTL_SYSPLLCFG0_ENABLECLK1_MASK |
            SYSCTL_SYSPLLCFG0_ENABLECLK0_MASK |
            SYSCTL_SYSPLLCFG0_MCLK2XVCO_MASK));

    // enable SYSPLL
    SYSCTL->SOCLOCK.HSCLKEN |= SYSCTL_HSCLKEN_SYSPLLEN_ENABLE;

    // wait until SYSPLL startup is stabilized
    while ((DL_SYSCTL_getClockStatus() & SYSCTL_CLKSTATUS_SYSPLLGOOD_MASK) !=
           DL_SYSCTL_CLK_STATUS_SYSPLL_GOOD) {
        ;
    }
}

2️⃣ With Default Code + Your Suggested Changes

void DL_SYSCTL_configSYSPLL(DL_SYSCTL_SYSPLLConfig *config)
{
    /* PLL configurations are retained in lower reset levels. Set default
     * behavior of disabling the PLL to keep a consistent behavior regardless
     * of reset level. */
    DL_SYSCTL_disableSYSPLL();

    /* Check that SYSPLL is disabled before configuration */
    while ((DL_SYSCTL_getClockStatus() & (DL_SYSCTL_CLK_STATUS_SYSPLL_OFF)) !=
           (DL_SYSCTL_CLK_STATUS_SYSPLL_OFF)) {
        ;
    }

    // set SYSPLL reference clock
    DL_Common_updateReg(&SYSCTL->SOCLOCK.SYSPLLCFG0,
        ((uint32_t) config->sysPLLRef), SYSCTL_SYSPLLCFG0_SYSPLLREF_MASK);

    // set predivider PDIV (divides reference clock)
    DL_Common_updateReg(&SYSCTL->SOCLOCK.SYSPLLCFG1, ((uint32_t) config->pDiv),
        SYSCTL_SYSPLLCFG1_PDIV_MASK);

    // save CPUSS CTL state and disable the cache
    uint32_t ctlTemp = DL_CORE_getInstructionConfig();
    DL_CORE_configInstruction(DL_CORE_PREFETCH_ENABLED, DL_CORE_CACHE_DISABLED,
        DL_CORE_LITERAL_CACHE_ENABLED);

    // populate SYSPLLPARAM0/1 tuning registers from flash, based on input freq
    SYSCTL->SOCLOCK.SYSPLLPARAM0 =
        *(volatile uint32_t *) ((uint32_t) config->inputFreq);
    SYSCTL->SOCLOCK.SYSPLLPARAM1 =
        *(volatile uint32_t *) ((uint32_t) config->inputFreq + (uint32_t) 0x4);

    // restore CPUSS CTL state
    CPUSS->CTL = ctlTemp;

    // set feedback divider QDIV (multiplies to give output frequency)
    DL_Common_updateReg(&SYSCTL->SOCLOCK.SYSPLLCFG1,
        ((config->qDiv << SYSCTL_SYSPLLCFG1_QDIV_OFS) &
            SYSCTL_SYSPLLCFG1_QDIV_MASK),
        SYSCTL_SYSPLLCFG1_QDIV_MASK);

    // write clock output dividers, enable outputs, and MCLK source to SYSPLLCFG0
    DL_Common_updateReg(&SYSCTL->SOCLOCK.SYSPLLCFG0,
        (((config->rDivClk2x << SYSCTL_SYSPLLCFG0_RDIVCLK2X_OFS) &
             SYSCTL_SYSPLLCFG0_RDIVCLK2X_MASK) |
            ((config->rDivClk1 << SYSCTL_SYSPLLCFG0_RDIVCLK1_OFS) &
                SYSCTL_SYSPLLCFG0_RDIVCLK1_MASK) |
            ((config->rDivClk0 << SYSCTL_SYSPLLCFG0_RDIVCLK0_OFS) &
                SYSCTL_SYSPLLCFG0_RDIVCLK0_MASK) |
            config->enableCLK2x | config->enableCLK1 | config->enableCLK0 |
            (uint32_t) config->sysPLLMCLK),
        (SYSCTL_SYSPLLCFG0_RDIVCLK2X_MASK | SYSCTL_SYSPLLCFG0_RDIVCLK1_MASK |
            SYSCTL_SYSPLLCFG0_RDIVCLK0_MASK |
            SYSCTL_SYSPLLCFG0_ENABLECLK2X_MASK |
            SYSCTL_SYSPLLCFG0_ENABLECLK1_MASK |
            SYSCTL_SYSPLLCFG0_ENABLECLK0_MASK |
            SYSCTL_SYSPLLCFG0_MCLK2XVCO_MASK));

    // enable SYSPLL
    SYSCTL->SOCLOCK.HSCLKEN |= SYSCTL_HSCLKEN_SYSPLLEN_ENABLE;

    // wait until SYSPLL startup is stabilized
    while ((DL_SYSCTL_getClockStatus() & SYSCTL_CLKSTATUS_SYSPLLGOOD_MASK) !=
           DL_SYSCTL_CLK_STATUS_SYSPLL_GOOD) {
        ;
    }
     SYSCTL->SOCLOCK.SYSPLLCFG0 |= SYSCTL_SYSPLLCFG0_MCLK2XVCO_ENABLE;   // (11) CLK2X->HSCLK: this is the only change I added extra
}

Based on this, I have doubts about whether the initialization sequence is correct. Could you please review it?

Another point from my side.

Need to confirm whether this is caused by SYSPLL or SYSOSC.

Could you please test SYSOSC without SYSPLL? Set CPU running at 32MHz directly source from SYSOSC.

I guess this is caused by SYSPLL configuration sequence, not about SYSOSC accuracy.

Vivek Chitte said:

Based on this, I have doubts about whether the initialization sequence is correct. Could you please review it?

I will review this, but this may take a few days to finish.

And It's great to receive such feedback from you.

Helic Chi said:

guess this is caused by SYSPLL configuration sequence, not about SYSOSC accuracy.

Vivek Chitte said:

I also doubt the SYSPLL initialization sequence, not the SYSOSC accuracy.

Vivek Chitte said:

I also doubt the SYSPLL initialization sequence, not the SYSOSC accuracy.

Agree with you.

This is a somewhat surprising result. What I observed -- indeed the premise of this thread -- was that once the PLL was started (PLLEN) the MCLK2XVCO bit (probably all of PLLCFG0) was locked and couldn't be updated. The implication would be that your additional line of code would have no effect. (Also: by then MCLK2XVCO was already set.) Is it possible that the Read (of the Read/Modify/Write) had an effect? [It's not supposed to, but I've been doing this stuff too long to automatically reject this idea.]

If you look near the end of the code I posted above, there's a clk_mon() function you might want to steal. The CLK_OUT function can monitor SYOSC or PLLOUT1 [you'll have to enable that one in Sysconfig] on PB11.

Here are some reference from TRM, but these seems not detailed enough:

Enabling and Disabling the SYSPLL
After configuration, enable the SYSPLL by setting the SYSPLLEN bit in the HSCLKEN register. Before enabling
the SYSPLL, make sure that the SYSPLL is in a disabled state by verifying that the SYSPLLOFF bit in the
CLKSTATUS register is set. After the SYSPLL is enabled, application software must not disable it until the
SYSPLLGOOD or SYSPLLOFF bit is set in the CLKSTATUS register, indicating that the SYSPLL transitioned to
a stable active state or a stable dead state. When the SYSPLL is enabled, the SYSPLL reference clock selection
must not be changed.

Quite busy now, but I am sure that I will verify this in next few days.