TMS570LC4357: Dual mcu core and its behaviour

Hi LayEng,

The lockstep is the mode of operation of the dual ARM Cortex-R5F CPUs. The device has one module called CCM-R5F. During CPU lockstep mode, the outputs of the two CPUs are compared on each CPU clock cycle by this module. Any mis-compare is flagged as an error of the highest severity level. The outputs of the two VIMs in lockstep are also compared on each cycle by this module.

The two processors are initialized to the same state during system start-up, and they receive the same inputs, so during normal operation the state of the two processors is identical from clock to clock.

An error in either processor will cause a difference between the states of the two processors, which will eventually be manifested as a difference in the outputs. The CCM-R4F module monitors the outputs of the two processors and flags an error in the case of a discrepancy.

LayEng Chan said:

Is it possible to let the checker mcu take over the operation should there be errors in the bus compare output.

No, the checker MCU will never takeover the operation. And if there is any mismatch in comparison, then even CCM module will also don't know which core produces error. The CCM module can only perform output comparison and if it founds any mismatch in outputs then it will flag the error. If there is a level-3 CCM error, then it can produce exception as well.

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Thanks & regards,
Jagadish.

Dear Jagadish

We thought that using TMS570LC4357 with its dual core will provide redundancy as required for rail operation. But it seems that is not the case with this dual core? Is it possible to switch to checker mcu to run the code at any reset? If it is possible, at least we can claim some redundancy. Looking forward to your reply. Thank you