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Extract of clocktree.json file "corrected" (not possible to enclose the .json file to the ticket, nor push all text content...)

"register_name":"PLL1_DIV_CTRL",
"offset":"0x1038",
"length":1,
"size":32,
"ldesc":"",
"sdesc":"PLL1_DIV_CTRL - PLL1 Output Clock Divider Register",
"reset_value":16908289,
"bitfields":[{"name":"POST_DIV1",
"access_type":"R/W",
"ldesc":"Primary post divider. To ensure correct operation,
post_div1 must always be programmed to a\nvalue equal to or greater that post_div2. Supports values of 1-7i\n\n Field values (Others are reserved):\n 3'b000 - Reserved (do not use)\n 3'b001 - Divide by 1\n 3'b010 - Divide by 2\n 3'b011 - Divide by 3\n 3'b100 - Divide by 4\n 3'b101 - Divide by 5\n 3'b110 - Divide by 6\n 3'b111 - Divide by 7",
"sdesc":"",
"reset_value":2,
"offset":16,
"size":3,
"enumerations":[1,
2,
3,
4,
5,
6,
7],
"selectable":true,
"description":"Bitfield Reset Value: 0x2\nBitfield Offset: 16\nPLL1_DIV_CTRL Register Address: 0x681038\nPLL1_DIV_CTRL Register Reset Value: 0x1020001\nRegister Description: PLL1_DIV_CTRL - PLL1 Output Clock Divider Register\nBitfield Description: Primary post divider. To ensure correct operation,
post_div1 must always be programmed to a value equal to or greater that post_div2. Supports values of 1-7i \n Field values (Others are reserved): 3'b000 - Reserved (do not use)\n: 3'b001 - Divide by 1\n: 3'b010 - Divide by 2\n: 3'b011 - Divide by 3\n: 3'b100 - Divide by 4\n: 3'b101 - Divide by 5\n: 3'b110 - Divide by 6\n: 3'b111 - Divide by 7",
"defaultValue":"2"},
{"name":"POST_DIV2",
"access_type":"R/W",
"ldesc":"Secondary post divider. Supports values of 1-7",
"sdesc":"",
"reset_value":1,
"offset":24,
"size":3,
"enumerations":[1,
2,
3,
4,
5,
6,
7],
"selectable":true,
"description":"Bitfield Reset Value: 0x1\nBitfield Offset: 24\nPLL1_DIV_CTRL Register Address: 0x681038\nPLL1_DIV_CTRL Register Reset Value: 0x1020001\nRegister Description: PLL1_DIV_CTRL - PLL1 Output Clock Divider Register\nBitfield Description: Secondary post divider. Supports values of 1-7",
"defaultValue":"1"},
{"name":"REF_DIV",
"access_type":"R/W",
"ldesc":"Reference clock pre-divider. Supports values of 1-63\n 6'b000000 - Reserved /(do not use/)\n 6'b000001 - Divide by 1\n 6'b000010 - Divide by 2\n :\n 6'b111111 - Divide by 63",
"sdesc":"",
"reset_value":1,
"offset":0,
"size":6,
"enumerations":[1,
2,
3,
4,
5,
6,
7,
8,
9,
10,
11,
12,
13,
14,
15,
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26,
27,
28,
29,
30,
31,
32,
33,
34,
35,
36,
37,
38,
39,
40,
41,
42,
43,
44,
45,
46,
47,
48,
49,
50,
51,
52,
53,
54,
55,
56,
57,
58,
59,
60,
61,
62,
63],
"selectable":true,
"description":"Bitfield Reset Value: 0x1\nBitfield Offset: 0\nPLL1_DIV_CTRL Register Address: 0x681038\nPLL1_DIV_CTRL Register Reset Value: 0x1020001\nRegister Description: PLL1_DIV_CTRL - PLL1 Output Clock Divider Register\nBitfield Description: Reference clock pre-divider. Supports values of 1-63\n: 6'b000000 - Reserved (do not use)\n: 6'b000001 - Divide by 1\n: 6'b000010 - Divide by 2\n: 6'b111111 - Divide by 63",
"defaultValue":"1"}]},