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MSPM0G3507: Timer in compare mode issue when value compared equals 0

Part Number: MSPM0G3507

Tool/software:

Hello,

I found an issue with timer specifically with compare mode and updating during zero event while trying to generate PWM signal. When comparing to value 0 (100% PWM duty cycle) signal value instead of being set to high stayed in low state (Fig1). Temporary fix was to instead 0 compare value has been set to 1 (Fig 2), but it is not an ideal scenario. Another idea to fix this issue was to change the update mode to immediate instead of zero event if compared value is equal to 0 (Fig 3), but this is also not a solution without disadvantages, main concern with this is that in case of an event that calculation performed in order to set applicable duty cycle are not fast enough to finish before next zero event that value is skipped when following value is 0.

This issue persists with changed polarity from CCP on compare up set to high to CCP on compare UP set to low.

Methodology to show this issue was to change compare value each period of a timer, from 0 to load value which is 833 with step of 83+/- 1 adjusting for int type. In figures channel 0 is complementary, channel 1 is main, channel 3 is GPIO toggled every instance of changing compare value. Timer used is TIMA1, configurated for center-aligned PWM and CCP set as output action on zero event, frequency of 48 kHz, load value 833

My question is if its normal for timer to misbehave when comparing to 0 or there is an setting for fixing that.

uint16_t instances_counter;
uint16_t compare_value;
uint32_t compare_values[] = {1, 83, 167, 250, 333, 416, 500, 583, 666, 750, 833};
uint32_t tabele_size = sizeof(compare_values)/sizeof(compare_values[0]);

void Timer_Duty_Change( void )
{
   if ( instances_counter < tabele_size)
   {
      compare_value = compare_values[instances_counter];
      instances_counter++;
   }
   else
   {
      instances_counter = 0;
   }

   TIMA1->COUNTERREGS.CC_01[ 1 ] = compare_value;
}

  • Hi,

    Thanks for your question.

    This issue could happen when the "Compare Counter(CC) value update event" and "CC value & counter value comparison event" happens at the same cycle. So if we set the duty cycle as zero and use zero event as CC updating trigger, this issue may occur.

    The way to avoid this is to make sure the CC register update and counter comparison with CC not occur at the same time. That is why if you set CC as 1 instead of 0 could temporary fix this issue. A workaround may be software force PWM output as low or high in 0% or 100% duty cycle by DL_Timer_overrideCCPOut() API. Please see TRM 27.2.5.3 Forced Output for more information.

  • So I assume correctly that it is a hardware issue, and if so are you going to add this to the Errata in next rev.?